SLASFA2B November   2024  – October 2025 MSPM0G1518 , MSPM0G1519 , MSPM0G3518 , MSPM0G3519

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Functional Block Diagram
  6. 5 Device Comparison
    1. 5.1 Device Comparison Chart
  7. 6 Pin Configuration and Functions
    1. 6.1 Pin Diagrams
    2. 6.2 Pin Attributes
      1.      11
    3. 6.3 Signal Descriptions
      1.      13
      2.      14
      3.      15
      4.      16
      5.      17
      6.      18
      7.      19
      8.      20
      9.      21
      10.      22
      11.      23
      12.      24
      13.      25
      14.      26
      15.      27
      16.      28
      17.      29
    4. 6.4 Connections for Unused Pins
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Supply Current Characteristics
      1. 7.5.1 RUN/SLEEP Modes
      2. 7.5.2 STOP/STANDBY Modes
      3. 7.5.3 SHUTDOWN Mode
    6. 7.6  Power Supply Sequencing
      1. 7.6.1 Power Supply Ramp
      2. 7.6.2 POR and BOR
    7. 7.7  Flash Memory Characteristics
    8. 7.8  Timing Characteristics
    9. 7.9  Clock Specifications
      1. 7.9.1 System Oscillator (SYSOSC)
      2. 7.9.2 Low Frequency Oscillator (LFOSC)
      3. 7.9.3 System Phase Lock Loop (SYSPLL)
      4. 7.9.4 Low Frequency Crystal/Clock
      5. 7.9.5 High Frequency Crystal/Clock
    10. 7.10 Digital IO
      1. 7.10.1  Electrical Characteristics
      2. 7.10.2 Switching Characteristics
    11. 7.11 Analog Mux VBOOST
    12. 7.12 ADC
      1. 7.12.1 Electrical Characteristics
      2. 7.12.2 Switching Characteristics
      3. 7.12.3 Linearity Parameters
      4. 7.12.4 Typical Connection Diagram
    13. 7.13 Temperature Sensor
    14. 7.14 VREF
      1. 7.14.1 Voltage Characteristics
      2. 7.14.2 Electrical Characteristics
    15. 7.15 Comparator (COMP)
      1. 7.15.1 Comparator Electrical Characteristics
    16. 7.16 DAC
      1. 7.16.1 DAC_Supply Specifications
      2. 7.16.2 DAC Output Specifications
      3. 7.16.3 DAC Dynamic Specifications
      4. 7.16.4 DAC Linearity Specifications
      5. 7.16.5 DAC Timing Specifications
    17. 7.17 I2C
      1. 7.17.1 I2C Characteristics
      2. 7.17.2 I2C Filter
      3. 7.17.3 I2C Timing Diagram
    18. 7.18 SPI
      1. 7.18.1 SPI
      2. 7.18.2 SPI Timing Diagram
    19. 7.19 UART
    20. 7.20 TIMx
    21. 7.21 TRNG
      1. 7.21.1 TRNG Electrical Characteristics
      2. 7.21.2 TRNG Switching Characteristics
    22. 7.22 Emulation and Debug
      1. 7.22.1 SWD Timing
  9. 8 Detailed Description
    1. 8.1  Functional Block Diagram
    2. 8.2  CPU
    3. 8.3  Operating Modes
      1. 8.3.1 Functionality by Operating Mode (MSPM0Gx51x)
    4. 8.4  Power Management Unit (PMU)
    5. 8.5  Clock Module (CKM)
    6. 8.6  DMA
    7. 8.7  Events
    8. 8.8  Memory
      1. 8.8.1 Memory Organization
      2. 8.8.2 Peripheral File Map
      3. 8.8.3 Peripheral Interrupt Vector
    9. 8.9  Flash Memory
    10. 8.10 SRAM
    11. 8.11 GPIO
    12. 8.12 IOMUX
    13. 8.13 ADC
    14. 8.14 Temperature Sensor
    15. 8.15 VREF
    16. 8.16 COMP
    17. 8.17 DAC
    18. 8.18 Security
    19. 8.19 TRNG
    20. 8.20 AESADV
    21. 8.21 Keystore
    22. 8.22 CRC-P
    23. 8.23 MATHACL
    24. 8.24 UART
    25. 8.25 I2C
    26. 8.26 SPI
    27. 8.27 CAN-FD
    28. 8.28 Low-Frequency Sub System (LFSS)
    29. 8.29 RTC_B
    30. 8.30 IWDT_B
    31. 8.31 WWDT
    32. 8.32 Timers (TIMx)
    33. 8.33 Device Analog Connections
    34. 8.34 Input/Output Diagrams
    35. 8.35 Serial Wire Debug Interface
    36. 8.36 Boot Strap Loader (BSL)
    37. 8.37 Device Factory Constants
    38. 8.38 Identification
  10. 9 Applications, Implementation, and Layout
    1. 9.1 Typical Application
      1. 9.1.1 Schematic
  11. 10Device and Documentation Support
    1. 10.1 Getting Started and Next Steps
    2. 10.2 Device Nomenclature
    3. 10.3 Tools and Software
    4. 10.4 Documentation Support
    5. 10.5 Support Resources
    6. 10.6 Trademarks
    7. 10.7 Electrostatic Discharge Caution
    8. 10.8 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Tray Information
    2.     PACKAGE OPTION ADDENDUM

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ZAW|100
  • PM|64
  • RGZ|48
  • RHB|32
  • PN|80
  • PZ|100
  • PT|48
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.9.1 System Oscillator (SYSOSC)

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fSYSOSC Factory trimmed SYSOSC frequency SYSOSCCFG.FREQ=00 (BASE) 32 MHz
SYSOSCCFG.FREQ=01 4
User trimmed SYSOSC frequency SYSOSCCFG.FREQ=10, SYSOSCTRIMUSER.FREQ=10 24
SYSOSCCFG.FREQ=10, SYSOSCTRIMUSER.FREQ=01 16
fSYSOSC SYSOSC frequency accuracy when frequency correction loop (FCL) is enabled and an ideal ROSC resistor is assumed (1) (2) SETUSEFCL=1, Ta = 25 ℃ -0.60 0.68 %
SETUSEFCL=1, -40 ℃ ≤ Ta ≤ 85 ℃ -0.80 0.93
SETUSEFCL=1, -40 ℃ ≤ Ta ≤ 105 ℃ -0.80 1.1
SETUSEFCL=1, -40 ℃ ≤ Ta ≤ 125 ℃ -0.80 1.3
fSYSOSC SYSOSC accuracy when frequency correction loop (FCL) is enabled with ROSC resistor put at ROSC pin, for factory trimmed frequencies(1)(5)(6) SETUSEFCL=1, Ta = 25 ℃, ±0.1% ±25ppm ROSC -0.7 0.78 %
SETUSEFCL=1, -40 ℃ ≤ Ta ≤ 85 ℃, ±0.1% ±25ppm ROSC -1.1 1.2
SETUSEFCL=1, -40 ℃ ≤ Ta ≤ 105 ℃, ±0.1% ±25ppm ROSC -1.1 1.4
SETUSEFCL=1, -40 ℃ ≤ Ta ≤ 125 ℃, ±0.1% ±25ppm ROSC -1.1 1.7
fSYSOSC SYSOSC frequency accuracy when frequency correction loop (FCL) is enabled when the internal ROSC resistor is used, 32MHz(4)(5)(6) SETUSEFCL=1, Ta = 25 ℃ -1.2 1.3 %
SETUSEFCL=1, -40 ℃ ≤ Ta ≤ 125 ℃ -2.1 1.6
fSYSOSC SYSOSC frequency accuracy when frequency correction loop (FCL) is enabled when the internal ROSC resistor is used, 4MHz(4)(5)(6) SETUSEFCL=1, Ta = 25 ℃ -1.2 1.7 %
SETUSEFCL=1, -40 ℃ ≤ Ta ≤ 125 ℃ -2.3 1.8
fSYSOSC SYSOSC accuracy when frequency correction loop (FCL) is disabled, 32MHz(5)(6) SETUSEFCL=0, SYSOSCCFG.FREQ=00, -40 ℃ ≤ Ta ≤ 125 ℃ -2.6 1.8 %
fSYSOSC SYSOSC accuracy when frequency correction loop (FCL) is disabled, for factory trimmed frequencies, 4MHz(5)(6) SETUSEFCL=0, SYSOSCCFG.FREQ=01, -40 ℃ ≤ Ta ≤ 125 ℃ -2.8 2.1 %
ROSC External resistor put between ROSC pin and VSS (1) SETUSEFCL=1 100 kΩ
tsettle, SYSOSC Settling time to target accuracy (3) SETUSEFCL=1, ±0.1% 25ppm ROSC  (1) 30 us
fsettle, SYSOSC fSYSOSC additional undershoot accuracy during tsettle (3) SETUSEFCL=1, ±0.1% 25ppm ROSC  (1) -16 %
(1) The SYSOSC frequency correction loop (FCL) enables high SYSOSC accuracy via an external reference resistor (ROSC) which must be connected between the device ROSC pin and VSS when using the FCL.  Accuracies are shown for a ±0.1% ±25ppm ROSC; relaxed tolerance resistors may also be used (with reduced SYSOSC accuracy).  See the SYSOSC section of the technical reference manual for details on computing SYSOSC accuracy for various ROSC accuracies.  ROSC does not need to be populated if the FCL is not enabled.
(2) Represents the device accuracy only.  The tolerance and temperature drift of the ROSC resistor used must be combined with this spec to determine final accuracy.  Performance for a ±0.1% ±25ppm ROSC is given as a reference point.
(3) When SYSOSC is waking up (for example, when exiting a low power mode) and FCL is enabled, the SYSOSC will initially undershoot the target frequency fSYSOSC by an additional error of up to fsettle,SYSOSC for the time tsettle,SYSOSC, after which the target accuracy is achieved.
(4) The SYSOSC frequency correction loop (FCL) enables high SYSOSC accuracy via an internal reference resistor when using the FCL. See the SYSOSC section of the technical reference manual for details on computing SYSOSC accuracy.
(5) SYSOSC Accuracy is measured in the default power-up state, with MCLK = SYSOSC, the CPU is running a while(1) loop, and the SYSPLL is disabled.
(6) SYSOSC is measured with the internal FCC counter using an external 1ms pulse as the measurement trigger.