JAJSQ88 データシート

JAJSQ88E february 2006 – october 2020 SN65LVDS301

PRODUCTION DATA

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）

ZXH|80
- MPBGAI9

サーマルパッド・メカニカル・データ

発注情報

6.8 Timing Characteristics

PARAMETER		TEST CONDITIONS	UNIT
t_PPOSX	Output Pulse Position, ⇅serial data to ↑CLK; see ⁽¹⁾ ⁽²⁾and Figure 7-6	1ChM: x=0..29, f_PCLK=15 MHz; TXEN at V_DD, V_IH=V_DD, V_IL=GND, R_L=100 Ω, test pattern as in Table 7-7 ⁽³⁾	ps
		1ChM: x=0..29, f_PCLK=4 MHz to 15 MHz ⁽⁴⁾
		2ChM: x = 0..14, f_PCLK = 30 MHz TXEN at V_DD, V_IH=V_DD, V_IL=GND, R_L=100 Ω, test pattern as in Table 7-8 ⁽³⁾
		2ChM: x=0..14, f_PCLK= 8 MHz to 30 MHz ⁽⁴⁾
		3ChM: x=0..9, f_PCLK=65 MHz, TXEN at V_DD, V_IH=V_DD, V_IL=GND, R_L=100 Ω, test pattern as in Table 7-9 ⁽³⁾
		3ChM: x=0..9, f_PCLK=20 MHz to 65 MHz ⁽⁴⁾

(1) This number also includes the high-frequency random and deterministic PLL clock jitter that is not traceable by the SN65LVDS302 receiver PLL; tPPosx represents the total timing uncertainty of the transmitter necessary to calculate the jitter budget when combined with the SN65LVDS302 receiver;

(2) The pulse position min/max variation is given with a bit error rate target of 10^–12; The measurement estimates the random jitter contribution to the total jitter contribution by multiplying the random RMS jitter by the factor 14; Measurements of the total jitter are taken over a sample amount of > 10^–12 samples.

(3) The Minimum and Maximum Limits are based on statistical analysis of the device performance over process, voltage, and temp ranges. This parameter is functionality tested only on Automatic Test Equipment (ATE).

(4) These Minimum and Maximum Limits are simulated only.