SPRABJ8D September   2022  – May 2025 AM2612 , AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1 , AM263P2 , AM263P2-Q1 , AM263P4 , AM263P4-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
  5. 2 Power
    1. 2.1 Discrete DC-DC Power Solution
    2. 2.2 Integrated PMIC Power Solution
    3. 2.3 Power Decoupling and Filtering
      1. 2.3.1 ADC/DAC Voltage Reference Decoupling
    4. 2.4 Estimated Power Consumption
    5. 2.5 Power Distribution Network
      1. 2.5.1 Simulations
        1. 2.5.1.1 Core Digital Power 1.2V
        2. 2.5.1.2 Digital and Analog I/O Power 3.3V
    6. 2.6 eFuse Power
  6. 3 Clocking
    1. 3.1 Crystal and Oscillator Input Options
    2. 3.2 Output Clock Generation
    3. 3.3 Crystal Selection and Shunt Capacitance
    4. 3.4 Crystal Placement and Routing
  7. 4 Resets
  8. 5 Bootstrapping
    1. 5.1 SOP Signal Implementation
  9. 6 OSPI and QSPI Memory Implementation
    1. 6.1 ROM OSPI and QSPI Boot Requirements
      1. 6.1.1 AM263x QSPI Boot Pin Requirements
      2. 6.1.2 AM263Px OSPI and QSPI Boot Pin Requirements
      3. 6.1.3 AM261x OSPI and QSPI Boot Pin Requirements
    2. 6.2 Additional OSPI and QSPI References
  10. 7 Debug Interfaces
    1. 7.1 JTAG Emulators and Trace
    2. 7.2 UART
  11. 8 USB
    1. 8.1 USB Device Mode
    2. 8.2 USB Host Mode
  12. 9 Multiplexed Peripherals
  13. 10Digital Peripherals
    1. 10.1 General Digital Peripheral Routing Guidelines
    2. 10.2 Trace Length Matching
  14. 11Analog Peripherals
    1. 11.1 General Analog Peripheral Routing Guidelines
      1. 11.1.1 Resolver ADC Routing Guidelines
  15. 12Layer Stackup
    1. 12.1 Key Stackup Features
  16. 13Vias
  17. 14BGA Power Fan-Out and Decoupling Placement
    1. 14.1 Ground Return
      1. 14.1.1 Ground Return - ZCZ Package AM26x Devices
      2. 14.1.2 Ground Return - ZNC and ZFG Package AM261x Devices
    2. 14.2 1.2V Core Digital Power
      1. 14.2.1 1.2V Core Digital Power Key Layout Considerations - ZCZ
      2. 14.2.2 1.2V Core Digital Power Key Layout Considerations - ZFG
    3. 14.3 3.3V Digital and Analog Power
      1. 14.3.1 3.3V I/O Power Key Layout Considerations - ZCZ
      2. 14.3.2 3.3V I/O Power Key Layout Considerations - ZFG
    4. 14.4 1.8V Digital and Analog Power
      1. 14.4.1 1.8V Key Layout Considerations - ZCZ
      2. 14.4.2 1.8V Key Layout Considerations - ZFG
  18. 15Summary
  19. 16References
  20. 17Revision History

6.1.2 AM263Px OSPI and QSPI Boot Pin Requirements

The following pins are configured in the device boot ROM to enable boot from the OSPI (or QSPI) flash device. These pins must be used in the connection between the AM263Px MCU and flash device.

Table 6-5 AM263Px OSPI Pins Configured in Boot ROM
Package Name Function Name GPIO # PinMux Mode #
QSPI0_CSn0 QSPI0_CSn0 0 0
QSPI0_CLK0 QSPI0_CLK0 2 0
QSPI0_D0 QSPI0_D0 3 0
QSPI0_D1 QSPI0_D1 4 0
QSPI0_D2 QSPI0_D2 5 0
QSPI0_D3 QSPI0_D3 6 0
MCAN0_RX OSPI0_D4 7 2
MCAN0_TX OSPI0_D5 8 2
MCAN1_RX OSPI0_D6 9 2
MCAN1_TX OSPI0_D7 10 2

AM263Px OSPI Reset

The AM263Px can reset an OSPI flash device using the dedicated OSPI0_RESET_OUT mux mode on GPIO20, GPIO66, or GPIO64. On the AM263Px controlCARD, the on-board OSPI flash reset signal is generated from the output of an AND gate with PORz and OSPI0_RESET_OUT0 as inputs. This method allows the flash device to be reset when the AM263Px device is power cycled, or through a software reset command.

AM263Px OSPI Reset Scheme Figure 6-6 AM263Px OSPI Reset Scheme

For the AM263Px SIP (Silicon-In-Package) device, the boot ROM configures the internal device pads connected to the on-die OSPI flash for boot.

Table 6-6 AM263Px-SIP Package OSPI Pins Configured in Boot ROM
Package Name Function Name GPIO # PinMux Mode #
QSPI0_CSn0(1) QSPI0_CSn0 65 6
QSPI0_CLK0(1) QSPI0_CLK0 9 6
QSPI0_D0(1) QSPI0_D0 0 6
QSPI0_D1(1) QSPI0_D1 66 6
QSPI0_D2(2) QSPI0_D2 8 6
QSPI0_D3(1) QSPI0_D3 69 6
MCAN0_RX(1) OSPI0_D4 6 6
MCAN0_TX(1) OSPI0_D5 67 6
MCAN1_RX(1) OSPI0_D6 5 6
MCAN1_TX(1) OSPI0_D7 68 6
GPIO7(1) OSPI0_DQS 7 6
GPIO70(1) OSPI0_ECC_FAIL 70 6
GPIO64(3) OSPI0_RESET_OUT0 64 5
(1) Each of these pins must be left unconnected with no PCB trace
(2) This pin must be connected to VDDS33 through a separate external 4.7kΩ pull resistor placed as close to the device as possible
(3) To reset the on-die OSPI flash module, OSPI_RESET_OUT0 must be connected to an open-drain equivalent of PORz.

AM263Px-SIP OSPI Reset

The AM263Px-SIP OSPI flash reset is generated using an open-drain version of PORz connected to the dedicated OSPI0_RESET_OUT0 pin configured by the device boot ROM. One method of implementing this is connecting the AM263Px-SIP PORz signal to the gate of a P-channel MOSFET, and connecting the source to the OSPI0_RESET_OUT0 (GPIO64) pin on the AM263Px-SIP MCU, with a 10kΩ pull-up resistor connected to this net. The drain of the P-channel MOSFET is to be connected to GND.