SPRABJ8D September   2022  – May 2025 AM2612 , AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1 , AM263P2 , AM263P2-Q1 , AM263P4 , AM263P4-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
  5. 2 Power
    1. 2.1 Discrete DC-DC Power Solution
    2. 2.2 Integrated PMIC Power Solution
    3. 2.3 Power Decoupling and Filtering
      1. 2.3.1 ADC/DAC Voltage Reference Decoupling
    4. 2.4 Estimated Power Consumption
    5. 2.5 Power Distribution Network
      1. 2.5.1 Simulations
        1. 2.5.1.1 Core Digital Power 1.2V
        2. 2.5.1.2 Digital and Analog I/O Power 3.3V
    6. 2.6 eFuse Power
  6. 3 Clocking
    1. 3.1 Crystal and Oscillator Input Options
    2. 3.2 Output Clock Generation
    3. 3.3 Crystal Selection and Shunt Capacitance
    4. 3.4 Crystal Placement and Routing
  7. 4 Resets
  8. 5 Bootstrapping
    1. 5.1 SOP Signal Implementation
  9. 6 OSPI and QSPI Memory Implementation
    1. 6.1 ROM OSPI and QSPI Boot Requirements
      1. 6.1.1 AM263x QSPI Boot Pin Requirements
      2. 6.1.2 AM263Px OSPI and QSPI Boot Pin Requirements
      3. 6.1.3 AM261x OSPI and QSPI Boot Pin Requirements
    2. 6.2 Additional OSPI and QSPI References
  10. 7 Debug Interfaces
    1. 7.1 JTAG Emulators and Trace
    2. 7.2 UART
  11. 8 USB
    1. 8.1 USB Device Mode
    2. 8.2 USB Host Mode
  12. 9 Multiplexed Peripherals
  13. 10Digital Peripherals
    1. 10.1 General Digital Peripheral Routing Guidelines
    2. 10.2 Trace Length Matching
  14. 11Analog Peripherals
    1. 11.1 General Analog Peripheral Routing Guidelines
      1. 11.1.1 Resolver ADC Routing Guidelines
  15. 12Layer Stackup
    1. 12.1 Key Stackup Features
  16. 13Vias
  17. 14BGA Power Fan-Out and Decoupling Placement
    1. 14.1 Ground Return
      1. 14.1.1 Ground Return - ZCZ Package AM26x Devices
      2. 14.1.2 Ground Return - ZNC and ZFG Package AM261x Devices
    2. 14.2 1.2V Core Digital Power
      1. 14.2.1 1.2V Core Digital Power Key Layout Considerations - ZCZ
      2. 14.2.2 1.2V Core Digital Power Key Layout Considerations - ZFG
    3. 14.3 3.3V Digital and Analog Power
      1. 14.3.1 3.3V I/O Power Key Layout Considerations - ZCZ
      2. 14.3.2 3.3V I/O Power Key Layout Considerations - ZFG
    4. 14.4 1.8V Digital and Analog Power
      1. 14.4.1 1.8V Key Layout Considerations - ZCZ
      2. 14.4.2 1.8V Key Layout Considerations - ZFG
  18. 15Summary
  19. 16References
  20. 17Revision History

6 OSPI and QSPI Memory Implementation

The OSPI Flash memory interface is the primary bootloader memory location for the AM263Px and AM261x MCUs, and the QSPI Flash memory interface is the primary bootloader memory location for the AM263x MCU. For a full description of boot ROM execution, including OSPI and QSPI boot information, see the device specific AM26x Technical Reference Manual. The correct OSPI and QSPI pins configured by the AM26x boot ROM are connected to the flash memory device if the intention is to boot from the flash.. Refer to Section 6.1 for additional details

The excerpt from Figure 6-1 shows the implementation of the QSPI NOR flash interface from the LP-AM263 design.

Example AM263x QSPI Controller and NOR Flash Memory Schematic Figure 6-1 Example AM263x QSPI Controller and NOR Flash Memory Schematic

The excerpt from Figure 6-2 shows the implementation of the OSPI NOR flash interface on the TMDSCNCD263P AM263Px controlCARD design.

Example AM263Px OSPI Controller and NOR Flash Memory Schematic Figure 6-2 Example AM263Px OSPI Controller and NOR Flash Memory Schematic

Series Termination Resistors

To control OSPI and QSPI bus transition overshoot and undershoot, include 22Ω series termination resistors close to the OSPI and QSPI memory pins. The OSPI_D[7:1] and QSPI_D[3:1] bits of the interface are used as a read interface and series termination resistors are used at the memory side of the bus. OSPI and QSPI_D0 can benefit from termination resistors at both the MCU side and the OSPI and QSPI memory side of the bus when used as both a single-mode write and part of single-mode and octal and quad-mode reads. However, placement of additional termination on both sides of this bus can be difficult to achieve from a PCB floor-planning perspective. The termination scheme presented here must be used as a minimum recommendation.

Power - AM261x ZFG, ZEJ, ZNC

AM263x, AM263Px, and AM261x ZCZ package devices are only capable of 3.3V-IO flash.

AM261x ZFG, ZEJ, ZNC are capable of operating flash in the 3.3V and 1.8V-IO domains. The flash IO level is set by supplying the corresponding power nets with the proper IO voltage - 3.3V or 1.8V:

Table 6-1 AM261x ZFG, ZEJ, ZNC Flash Power Nets
Power Rail Device Power Net Corresponding OSPI Peripheral
VDDSHV_D FLASH0 OSPI0
VDDSHV_E FLASH1 OSPI1

For example, if the OSPI device connected to OSPI0 operates at 1.8V logic, then connect a 1.8V to the VDDSHV_D pins on the AM261x device. If OSPI1 operates at 3.3V logic, then connect a 3.3V supply to the VDDSHV_E pins on the AM261x device.

Pull Resistors - QSPI

Pull resistors are also necessary on the QSPI clock, chip-select, reset and data lines. Different OSPI/QSPI memories can have different pull-up/down requirements depending on the specific memory and application requirements. These pull resistor recommendations are based on the implementation of the S25FL128x memory used on the LP-AM263 design. To confirm all pin memory configuration details, see the device-specific QSPI Flash memory data sheet. Include the following pull resistors on the QSPI signals:

  • QSPI_CLK, QSPI_CS[1:0], and QSPI_D[1:0] - include 100kΩ pull-up to VDDS33 IO supply.
  • QSPI_D[2] - 10kΩ pull-up to VDDS33 IO supply. This disables write-protect mode on the S25FL128 flash memories.
  • QSPI_D[3] - 10kΩ pull-up to VDDS33 IO supply. This disables hold mode on the S25FL128 flash memories.

Pull Resistors - OSPI

Different OSPI memories have different pull-up and pull-down requirements depending on the specific memory and application requirements. These pull resistor recommendations are based on the implementation of the IS25LX256x memory used on the TMDSCNCD263P design. To confirm all pin memory configuration details, see the device specific OSPI Flash memory data sheet. Include the following pull resistors on the OSPI signals:

  • OSPI_CLK - include 100kΩ pull-down to GND
  • OSPI_CS - 10kΩ pull-up to IO supply
  • OSPI_DQS - 1kΩ pull-down to GND
  • OSPI_D[2] - 4.7kΩ pull-up to IO supply. This disables write-protect mode on the IS25LX256 flash memories
  • OSPI_D[1:0] and OSPI_D[7:3] - 49.9kΩ pull-up to IO supply
  • OSPI_RESETn - 10kΩ pull-up to IO supply

Stronger pull-up resistors are used to disable write-protect and hold modes by default. Weaker pull-up resistors are used to keep the lines at valid logic levels between transactions. Pull resistors must be placed close to the OSPI and QSPI memory pins to prevent any additional routing stubs from being formed.

Excerpt From LP-AM263 Launchpad Layout – Highlighting SOP0/QSPI_D0 Path and SOP Isolation Resistor Figure 6-3 Excerpt From LP-AM263 Launchpad Layout – Highlighting SOP0/QSPI_D0 Path and SOP Isolation Resistor

Additional routing guidelines for the QSPI memory interface are provided in Figure 6-4 and Table 6-2. These must be used as maximum routing delay and skew match limits. The QSPI memory must be placed close to the AM26x BGA footprint as possible. This allows for routing that maximizes the delay margins and skew margins and minimizes transmission-line effects.

AM26x QSPI - Routing Rules Diagram Figure 6-4 AM26x QSPI - Routing Rules Diagram

Additional routing guidelines for the OSPI memory interface are provided in Figure 6-5 and Table 6-3. These are used as maximum routing delay and skew match limits. The OSPI memory must be placed close to the AM263Px and AM261x BGA footprint as possible. This allows for routing that maximizes the delay margins and skew margins and minimizes transmission-line effects.

AM263Px. AM261x OSPI - Routing Rules Diagram Figure 6-5 AM263Px. AM261x OSPI - Routing Rules Diagram
Table 6-2 AM26x QSPI – Recommended Routing Rules
Spec No. Specification Value Unit
1 QSPI_CLK, QSPI_CS0, QSPI_D[3:0] maximum delay 450 ps
2 QSPI_CLK to QSPI_D[3:0] maximum skew 50 ps
3 Approximate maximum routing distances 3214 mils
4 Approximate maximum routing skew 357 mils
5 A series termination resistor (R1 in diagram above) must be placed close to the QSPI_CLK transmit pin of the AM263x, AM263Px, AM261x to control rise-time and reflections of the clock line. Variable, 0 to 40 Ω
6 A series termination resistor (R2 in diagram above) must be placed close to the QSPI data pins of the attached memory to control rise-time and reflections of the data lines. Variable, 0 to 40 Ω
Table 6-3 AM263Px, AM261x OSPI – Recommended Routing Rules
Spec No. Specification Value Unit
1 OSPI_CLK, OSPI_CS0, OSPI_D[7:0] maximum delay (1) 450 ps
2 OSPI_CLK to OSPI_D[7:0] and OSPI_CSn maximum skew 60 ps
3 OSPI_CLK to OSPI_DQS maximum skew 30 ps
4 Approximate maximum routing distances (1) 3214 mils
5 OSPI_CLK to OSPI_D[7:0] and OSPI_CSn approximate maximum routing skew 429 mils
6 OSPI_CLK to OSPI_DQS approximate maximum routing skew 214 mils
7 A series termination resistor (R1 in diagram above) must be placed close to the OSPI_CLK transmit pin of the AM263Px to control rise-time and reflections of the clock line. Variable, 0 to 40 Ω
8 Series termination resistor must be placed close to the OSPI data pins of the attached memory and the AM263Px device to control rise-time and reflections of the data lines. Variable, 0 to 40 Ω
(1) This routing limit is applicable only in Fixed Timing modes in Internal PHY Loopback, Internal Pad Loopback, or External Board Loopback clock topologies. This does not apply when using DQS Clocking topology.
Note: Approximate routing distances are computed assuming a typical 140ps/inch propagation delay in 50Ω FR4 Microstrip or Stripline transmission lines. A 2D field solver or appropriate closed-form approximate impedance model must be used to find more exact propagation delay for your specific stackup and routing.