SPRABJ8D September   2022  – May 2025 AM2612 , AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1 , AM263P2 , AM263P2-Q1 , AM263P4 , AM263P4-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
  5. 2 Power
    1. 2.1 Discrete DC-DC Power Solution
    2. 2.2 Integrated PMIC Power Solution
    3. 2.3 Power Decoupling and Filtering
      1. 2.3.1 ADC/DAC Voltage Reference Decoupling
    4. 2.4 Estimated Power Consumption
    5. 2.5 Power Distribution Network
      1. 2.5.1 Simulations
        1. 2.5.1.1 Core Digital Power 1.2V
        2. 2.5.1.2 Digital and Analog I/O Power 3.3V
    6. 2.6 eFuse Power
  6. 3 Clocking
    1. 3.1 Crystal and Oscillator Input Options
    2. 3.2 Output Clock Generation
    3. 3.3 Crystal Selection and Shunt Capacitance
    4. 3.4 Crystal Placement and Routing
  7. 4 Resets
  8. 5 Bootstrapping
    1. 5.1 SOP Signal Implementation
  9. 6 OSPI and QSPI Memory Implementation
    1. 6.1 ROM OSPI and QSPI Boot Requirements
      1. 6.1.1 AM263x QSPI Boot Pin Requirements
      2. 6.1.2 AM263Px OSPI and QSPI Boot Pin Requirements
      3. 6.1.3 AM261x OSPI and QSPI Boot Pin Requirements
    2. 6.2 Additional OSPI and QSPI References
  10. 7 Debug Interfaces
    1. 7.1 JTAG Emulators and Trace
    2. 7.2 UART
  11. 8 USB
    1. 8.1 USB Device Mode
    2. 8.2 USB Host Mode
  12. 9 Multiplexed Peripherals
  13. 10Digital Peripherals
    1. 10.1 General Digital Peripheral Routing Guidelines
    2. 10.2 Trace Length Matching
  14. 11Analog Peripherals
    1. 11.1 General Analog Peripheral Routing Guidelines
      1. 11.1.1 Resolver ADC Routing Guidelines
  15. 12Layer Stackup
    1. 12.1 Key Stackup Features
  16. 13Vias
  17. 14BGA Power Fan-Out and Decoupling Placement
    1. 14.1 Ground Return
      1. 14.1.1 Ground Return - ZCZ Package AM26x Devices
      2. 14.1.2 Ground Return - ZNC and ZFG Package AM261x Devices
    2. 14.2 1.2V Core Digital Power
      1. 14.2.1 1.2V Core Digital Power Key Layout Considerations - ZCZ
      2. 14.2.2 1.2V Core Digital Power Key Layout Considerations - ZFG
    3. 14.3 3.3V Digital and Analog Power
      1. 14.3.1 3.3V I/O Power Key Layout Considerations - ZCZ
      2. 14.3.2 3.3V I/O Power Key Layout Considerations - ZFG
    4. 14.4 1.8V Digital and Analog Power
      1. 14.4.1 1.8V Key Layout Considerations - ZCZ
      2. 14.4.2 1.8V Key Layout Considerations - ZFG
  18. 15Summary
  19. 16References
  20. 17Revision History

12.1 Key Stackup Features

Table 12-2 Stackup Features by Package Size
ZCZ (15mm x15mm, 0.8mm Pitch), ZFG (13.25mm x 13.25mm, 0.65mm Pitch) ZFG (13.25mm x 13.25mm, 0.65mm Pitch), ZNC (10mm x 10mm, 0.5mm Pitch)
Total Layers 6 4
PCB Thickness 62 mil +/- 10% 62 mil +/- 10%
Optionally Controlled Impedance Routing Layers 4 (L1, L3, L4, L6) 2 (L1, L4)
Signal/Power Layers have Adjacent GND Reference Yes Yes
Core Center Layer Thickness 28 mil 42 mil
BGA Fan-out Via Type Through-hole Through-hole
Note: In a 6-layer design, minimal dielectric thickness between L4 power and L5 GND return layers allows for best plane capacitance performance, aiding power integrity and EMI.
Table 12-3 6-Layer PCB: Layer Utilization
Layer Number Comment
Copper 1 (Top) Top layer mounting and signal routing
Copper 2 Ground return plane
Copper 3 Embedded microstrip or stripline signal routing and power routing
Copper 4 Embedded microstrip or stripline and power routing
Copper 5 Ground return plane
Copper 6 (Bottom) Bottom layer mounting and signal routing
Table 12-4 AM263x, AM263Px, AM261x ZCZ Package, 6-Layer PCB: Controlled Impedance Planning Options
Layer Number Reference Layer Number Structure Name (1) Trace Width (mils) Trace Separation (mils) Target Impedance (Ω) Calculated Impedance (Ω) Notes
L1 L2 Coated Microstrip 5.300 0.000 50.000 50.140
L1 L2 Edge Coupled Coated Microstrip 4.200 5.000 90.000 89.830 L1, USB differential
L1 L2 Edge Coupled Coated Microstrip 4.000 7.700 100.000 99.840
L1 L2 Edge Coupled Coated Microstrip 4.100 6.800 120.000 120.030
L3 L3 Offset Stripline 4.750 0.000 50.000 49.960
L3 L2 Edge Coupled Offset Stripline 4.000 6.000 90.000 90.040 L3, USB differential
L3 L2 Edge Coupled Offset Stripline 3.500 8.100 100.000 99.880
L3 L2 Edge Coupled Offset Stripline 4.000 12.000 100.000 100.160
L6 L5 Coated Microstrip 5.300 0.000 50.000 50.140
L6 L5 Edge Coupled Coated Microstrip 4.200 5.000 90.000 89.830
L6 L5 Edge Coupled Coated Microstrip 4.000 7.700 100.000 99.840
L6 L4 Edge Coupled Coated Microstrip 4.100 6.800 120.000 120.030
Table 12-5 4-Layer PCB: Layer Utilization
Layer Number Comment
Copper 1 (Top) Top layer mounting and signal routing
Copper 2 Ground return plane
Copper 3 Power routing
Copper 4 (Bottom) Bottom layer mounting and signal routing
Table 12-6 AM261x ZFG Package, 4-Layer PCB: Controlled Impedance Planning Options
Layer Number Reference Layer Number Structure Name (1) Trace Width (mils) Trace Separation (mils) Target Impedance (Ω) Calculated Impedance (Ω) Notes
L1 L2 Coated Microstrip 4.000 3.900 50.000 49.640
L1 L2 Edge Coupled Coated Microstrip 4.200 5.800 90.000 93.700 L1, USB differential
L1 L2 Edge Coupled Coated Microstrip 4.000 7.700 100.000 99.840
L1 L2 Edge Coupled Coated Microstrip 4.100 6.800 120.000 120.030
L4 L3 Coated Microstrip 5 8.5 50.000 47.400
L4 L3 Edge Coupled Coated Microstrip 4.200 5.000 90.000 89.830
L4 L3 Edge Coupled Coated Microstrip 4.000 7.700 100.000 99.840
L4 L3 Edge Coupled Coated Microstrip 4.100 6.800 120.000 120.030
Table 12-7 AM261x ZNC Package, 4-Layer PCB: Controlled Impedance Planning Options
Layer Number Reference Layer Number Structure Name (1) Trace Width (mils) Trace Separation (mils) Target Impedance (Ω) Calculated Impedance (Ω) Notes
L1 L2 Coated Microstrip 3.200 3.300 50.000 52.960
L1 L2 Edge Coupled Coated Microstrip 4.200 5.800 90.000 93.700 L1, USB differential
L1 L2 Edge Coupled Coated Microstrip 4.000 7.700 100.000 99.840
L1 L2 Edge Coupled Coated Microstrip 4.100 6.800 120.000 120.030
L4 L3 Coated Microstrip 3.500 6.650 50.000 49.980
L4 L3 Edge Coupled Coated Microstrip 4.200 5.000 90.000 89.830
L4 L3 Edge Coupled Coated Microstrip 4.000 7.700 100.000 99.840
L4 L3 Edge Coupled Coated Microstrip 4.100 6.800 120.000 120.030
(1) All impedance calculated using Polar 2D field solver on given copper and dielectric thicknesses, widths and dissipation constants.