SBASAL2 November   2025 ADC32RF72

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics - Power Consumption
    6. 5.6 Electrical Characteristics - DC Specifications
    7. 5.7 Electrical Characteristics - AC Specifications
    8. 5.8 Timing Requirements
    9. 5.9 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Inputs
        1. 7.3.1.1 Input Bandwidth
        2. 7.3.1.2 Background Calibration
      2. 7.3.2 ADC Channel Selection and Power Down Modes
      3. 7.3.3 Sampling Clock Input
      4. 7.3.4 SYSREF
        1. 7.3.4.1 SYSREF Monitor
      5. 7.3.5 Digital Signal Processor (DSP) Features
        1. 7.3.5.1 DSP Input Mux
        2. 7.3.5.2 Fractional Delay
        3. 7.3.5.3 Programmable FIR Filter for Equalization
        4. 7.3.5.4 DSP Output Mux
        5. 7.3.5.5 Digital Down Converter (DDC)
          1. 7.3.5.5.1 Decimation Filter Input
          2. 7.3.5.5.2 Decimation Modes
          3. 7.3.5.5.3 Decimation Filter Response
          4. 7.3.5.5.4 Numerically Controlled Oscillator (NCO)
            1. 7.3.5.5.4.1 NCO Update
            2. 7.3.5.5.4.2 NCO RESET
      6. 7.3.6 Digital Output Interface
        1. 7.3.6.1 JESD204B/C Interface
          1. 7.3.6.1.1 JESD204B Initial Lane Alignment (ILA)
          2. 7.3.6.1.2 SYNC Signal
          3. 7.3.6.1.3 JESD204B/C Frame Assembly
          4. 7.3.6.1.4 JESD204B/C Frame Assembly in Bypass Mode
          5. 7.3.6.1.5 JESD204B/C Frame Assembly With Real Decimation
          6. 7.3.6.1.6 JESD204B,C Frame Assembly With Complex Decimation
        2. 7.3.6.2 JESD Output Reference Clock
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device Operating Mode Comparison
    5. 7.5 Programming
      1. 7.5.1 GPIO Control
      2. 7.5.2 SPI Register Write
      3. 7.5.3 SPI Register Read
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application: Spectrum Analyzer
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Input Signal Path: Wideband Receiver
        2. 8.2.1.2 Clocking
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Sampling Clock Requirements
      3. 8.2.3 Application Performance Plots
    3. 8.3 Typical Application: Time Domain Digitizer
      1. 8.3.1 Design Requirements
        1. 8.3.1.1 Input Signal Path: Time Domain Digitizer
      2. 8.3.2 Application Performance Plots
    4. 8.4 Initialization Set Up
    5. 8.5 Power Supply Recommendations
    6. 8.6 Layout
      1. 8.6.1 Layout Guidelines
      2. 8.6.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
      2. 9.1.2 Third-Party Products Disclaimer
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

7.3.6.1 JESD204B/C Interface

The ADC32RF7x uses the JESD204B/C high-speed serial interface to transfer data from the ADC to the receiving logic device. ADC32RF7x serialized lanes are capable of operating up to 24.75Gbps using JESD204C and up to 15Gbps using JESD204B. The device supports up to 2 JESD links (operated at the same lane rate) and lane options of 1,2,4 or 8 lanes. Figure 7-34 shows an internal block diagram of the JESD204 interface as well as the configuration parameters for each of the two links.

ADC32RF72 JESD204 Block DiagramFigure 7-34 JESD204 Block Diagram

The following parameters and constraints need to be considered when configuring the JESD204B/C interface.

Range of L, M, F, S, N and N'

  • L: Number of lanes: L ∈ {1,2,4,8}
  • M: Number of converters: M ∈ {1,2,4,8}; for M=16 (octal band decimation), the JESD interface needs to configured to 2 links with M=8 per link
  • F: Number of octets per frame: F ∈ {1,2,...,Fmax}
  • S: Number of samples per converter: S ∈ {1,2,4}
  • N': Sample resolution with padding: N' = 8⋅L⋅F/(M⋅S), and N' ∈ {16,24,32}
  • N: Sample resolution without padding: N' ∈ {16,24} and N <= N'

Constraints on F and N'

  • N' = 16 => Fmax = 64
  • N' ∈ {24,32} => Fmax = 64
  • N= 32 => F must be a multiple of 4.

Constraints on Number of Lanes (L) and Lane Rate (LR)

  • JESD TX lane rate LR: 4.0Gbps to 24.75Gbps

  • L = 8 is only allowed for JESD TX Link 0 and not for JESD TX link 1

Constraints on Decimation Factor (D) and Repeat Factor (R)

  • Sample repeat factor R = 2p, p ∈ ℕ+

  • D <= 4: R = 1
  • D%3 = 0: R = 1
  • D%5 = 0: R = 1
  • D > 4: D/R >= 4

Constraints on JESD TX Converter Selection

  • Selected converter C ∈ {0,1,...,19}, see Table 7-16

  • Converters can be presented in any order within the set above
  • In addition the constraints in Table 7-17 apply.

Table 7-16 Converter Selection
CONVERTERSELECTION NUMBER
DDC0_I0
DDC0_Q1
......
DDC7_Q15
ADC016
ADC117
Table 7-17 Valid JESD Configurations
JESD DATA MODEDECIMATION
FACTOR D		NUMBER OF CONVERTERS M PER LINKCONVERTERS AVAILABLE FOR SELECTIONCONVERTERS NUMBERS AVAILABLE FOR SELECTION
JESD_DATA_MODE_DSP_OUT1 (DDC BYPASS)1,2ADC0, ADC116,17
JESD_DATA_MODE_DDC_OUT2,31,2,4DDC0_IQ, DDC1_IQ, DDC4_IQ, DDC5_IQ0,1,2,3,8,9,10,11
4,51,2,4,8DDC0_IQ, ...DDC7_IQ0,1,2....14,15
8,16,32...
6,10,12,20,...

The following parameters can be programmed:

Table 7-18 JESD TX Link Registers (x: 0 = LINK0, 1 = LINK1)

System Parameter Name

SizeDefaultResetDescription
LINK{x}_SCR_EN10RW

Control the JESD scrambler enable.

0: JESD scrambler is disabled.

1: JESD scrambler is enabled.

LINK{x}_JESD_TYPE10RW

Select the JESD type and must be set identically to the ENCODING setting.

0: 8b10b

1: 64b66b

LINK{x}_ENCODING10RW

Select the JESD encoding. Must be set identically to the JESD_TYPE setting.

0: 8b10b encoding.

1: 64b66b encoding.

LINK{x}_JESD_DATA_MODE20RW

Select the JESD data source.

0: DDC_OUT provided to JESD.

1: DSP_OUT provided to JESD.

2: not used

3: not used

LINK{x}_JESD_LANES44RW

Set the JESD lanes (L) parameter for the link.

0: LINK is disabled.

1: JESD L parameter set to 1.

2: JESD L parameter set to 2.

4: JESD L parameter set to 4.

8: JESD L parameter set to 8.

LINK{x}_JESD_CONVERTERS42RW

Set the JESD converters (M) parameter for the link.

0: LINK is disabled.

1: JESD M parameter set to 1.

2: JESD M parameter set to 2.

4: JESD M parameter set to 4.

8: JESD M parameter set to 8.

LINK{x}_JESD_OCTETS_PER_FRAME71RW

Set the JESD octets per frame (F) parameter for the link. The max value is for F is 64. If N' is 32 then F must be a multiple of 4.

1...64: JESD F parameter value.

LINK{x}_JESD_SAMPLES_PER_CONVERTER31RW

Set the JESD samples per converter (S) parameter for the link.

1: JESD S parameter set to 1.

2: JESD S parameter set to 2.

4: JESD S parameter set to 4.

LINK{x}_JESD_K_OR_E832RW

Set either the JESD frames per multi-frame (K) or the multi-blocks per extended multi-block (E). This field is the K parameter when 8b10b encoding is used or E when 64b66b encoding is used.

LINK{x}_CONV_SEL_{y}516RW

Select the data source of the {y} converter in the link. (y=0..7)

0: DDC0 in-phase component data.

1: DDC0 quadrature component data.

2: DDC1 in-phase component data.

3: DDC1 quadrature component data.

4: DDC2 in-phase component data.

5: DDC2 quadrature component data.

6: DDC3 in-phase component data.

7: DDC3 quadrature component data.

8: DDC4 in-phase component data.

9: DDC4 quadrature component data.

10: DDC5 in-phase component data.

11: DDC5 quadrature component data.

12: DDC6 in-phase component data.

13: DDC6 quadrature component data.

14: DDC7 in-phase component data.

15: DDC7 quadrature component data.

16: ADC0 data from DSP_OUT.

17: ADC1 data from DSP_OUT.

18: ADC2 data from DSP_OUT.

19: ADC3 data from DSP_OUT.

JESD_SYNC_N_SRC_SEL20RW

Set the SYNC_N signal source for 8b10b.

0: GPIO0 used as SYNC_N input.

2: SYNC_N is internally generated through software.

JESD_PHY_LANE{y}_DATA_SEL30,1RW

Set the physical lane data source for the lane{y}. (y = 0..7).

0: JESD logical lane 0 used as the lane data.

1: JESD logical lane 1 used as the lane data.

2: JESD logical lane 2 used as the lane data.

3: JESD logical lane 3 used as the lane data.

4: JESD logical lane 4 used as the lane data.

5: JESD logical lane 5 used as the lane data.

6: JESD logical lane 6 used as the lane data.

7: JESD logical lane 7 used as the lane data.

JESD_PHY_LANE_POLARITY_CTRL80RW

Set the individual physical lane polarity. If the bit is set, the corresponding physical lane polarity is inverted.

Bit 0: JESD physical lane 0 polarity control.

Bit 1: JESD physical lane 1 polarity control.

Bit 2: JESD physical lane 2 polarity control.

Bit 3: JESD physical lane 3 polarity control.

Bit 4: JESD physical lane 4 polarity control.

Bit 5: JESD physical lane 5 polarity control.

Bit 6: JESD physical lane 6 polarity control.

Bit 7: JESD physical lane 7 polarity control.