SBASAL2 November   2025 ADC32RF72

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics - Power Consumption
    6. 5.6 Electrical Characteristics - DC Specifications
    7. 5.7 Electrical Characteristics - AC Specifications
    8. 5.8 Timing Requirements
    9. 5.9 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Inputs
        1. 7.3.1.1 Input Bandwidth
        2. 7.3.1.2 Background Calibration
      2. 7.3.2 ADC Channel Selection and Power Down Modes
      3. 7.3.3 Sampling Clock Input
      4. 7.3.4 SYSREF
        1. 7.3.4.1 SYSREF Monitor
      5. 7.3.5 Digital Signal Processor (DSP) Features
        1. 7.3.5.1 DSP Input Mux
        2. 7.3.5.2 Fractional Delay
        3. 7.3.5.3 Programmable FIR Filter for Equalization
        4. 7.3.5.4 DSP Output Mux
        5. 7.3.5.5 Digital Down Converter (DDC)
          1. 7.3.5.5.1 Decimation Filter Input
          2. 7.3.5.5.2 Decimation Modes
          3. 7.3.5.5.3 Decimation Filter Response
          4. 7.3.5.5.4 Numerically Controlled Oscillator (NCO)
            1. 7.3.5.5.4.1 NCO Update
            2. 7.3.5.5.4.2 NCO RESET
      6. 7.3.6 Digital Output Interface
        1. 7.3.6.1 JESD204B/C Interface
          1. 7.3.6.1.1 JESD204B Initial Lane Alignment (ILA)
          2. 7.3.6.1.2 SYNC Signal
          3. 7.3.6.1.3 JESD204B/C Frame Assembly
          4. 7.3.6.1.4 JESD204B/C Frame Assembly in Bypass Mode
          5. 7.3.6.1.5 JESD204B/C Frame Assembly With Real Decimation
          6. 7.3.6.1.6 JESD204B,C Frame Assembly With Complex Decimation
        2. 7.3.6.2 JESD Output Reference Clock
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device Operating Mode Comparison
    5. 7.5 Programming
      1. 7.5.1 GPIO Control
      2. 7.5.2 SPI Register Write
      3. 7.5.3 SPI Register Read
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application: Spectrum Analyzer
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Input Signal Path: Wideband Receiver
        2. 8.2.1.2 Clocking
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Sampling Clock Requirements
      3. 8.2.3 Application Performance Plots
    3. 8.3 Typical Application: Time Domain Digitizer
      1. 8.3.1 Design Requirements
        1. 8.3.1.1 Input Signal Path: Time Domain Digitizer
      2. 8.3.2 Application Performance Plots
    4. 8.4 Initialization Set Up
    5. 8.5 Power Supply Recommendations
    6. 8.6 Layout
      1. 8.6.1 Layout Guidelines
      2. 8.6.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
      2. 9.1.2 Third-Party Products Disclaimer
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

5.8 Timing Requirements

Maximum and minimum values are specified over the operating free-air temperature range and nominal supply voltages. Typical values are specified at TA = 25°C, ADC sampling rate = 1.5 GSPS, DDC Bypass mode, 50% clock duty cycle, nominal supply voltages and –1-dBFS differential input, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
ADC Timing Specifications
TAD Aperture Delay 0.15 ns
Aperture Delay variation 0.05 ns
TA Aperture Jitter 40 fs
CER Code error rate 1e-15 errors/sample
Wake up time time to valid data (SNR within 2dB of data sheet values) after coming out of fast power down (JESD stays active) 5 μs
LATENCY: tPD + tADC
tPD Propagation delay 1 ns
tADC ADC latency from sampling instant to JESD output DDC bypass, LMFS = 8411 524 ADC clock cycles
SERIAL PROGRAMMING INTERFACE (SCLK, SEN, SDIO) - Input
fCLK(SCLK) Serial clock frequency 1 50 MHz
tS(SEN) SEN to rising edge of SCLK 10 ns
tH(SEN) SEN from rising edge of SCLK 10 ns
tSU(SDIO) SDIO to rising edge of SCLK 10 ns
tH(SDIO) SDIO from rising edge of SCLK 10 ns
SERIAL PROGRAMMING INTERFACE (SDIO, SDOUT) - Output
t(OZD) SDIO tri-state to driven 10 ns
t(ODZ) SDIO data to tri-state 14 ns
t(OD) SDIO valid from falling edge of SCLK 10 ns
Timing: SYSREFP/N
ts(SYSREF) Setup time, SYSREFP/N valid to rising edge of CLKP/N 50 ps
th(SYSREF) Hold time, SYSREFP/N valid to rising edge of CLKP/N 50 ps
CML SerDes Outputs: STX[0..7]P/N
fSerdes SerDes bit rate 4.0 24.75 Gbps
RJ Random jitter 0.45 ps
DJ Deterministic jitter 12.5 ps
TJ Total jitter, peak-peak 19.7 ps