SBASAL2 November   2025 ADC32RF72

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics - Power Consumption
    6. 5.6 Electrical Characteristics - DC Specifications
    7. 5.7 Electrical Characteristics - AC Specifications
    8. 5.8 Timing Requirements
    9. 5.9 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Inputs
        1. 7.3.1.1 Input Bandwidth
        2. 7.3.1.2 Background Calibration
      2. 7.3.2 ADC Channel Selection and Power Down Modes
      3. 7.3.3 Sampling Clock Input
      4. 7.3.4 SYSREF
        1. 7.3.4.1 SYSREF Monitor
      5. 7.3.5 Digital Signal Processor (DSP) Features
        1. 7.3.5.1 DSP Input Mux
        2. 7.3.5.2 Fractional Delay
        3. 7.3.5.3 Programmable FIR Filter for Equalization
        4. 7.3.5.4 DSP Output Mux
        5. 7.3.5.5 Digital Down Converter (DDC)
          1. 7.3.5.5.1 Decimation Filter Input
          2. 7.3.5.5.2 Decimation Modes
          3. 7.3.5.5.3 Decimation Filter Response
          4. 7.3.5.5.4 Numerically Controlled Oscillator (NCO)
            1. 7.3.5.5.4.1 NCO Update
            2. 7.3.5.5.4.2 NCO RESET
      6. 7.3.6 Digital Output Interface
        1. 7.3.6.1 JESD204B/C Interface
          1. 7.3.6.1.1 JESD204B Initial Lane Alignment (ILA)
          2. 7.3.6.1.2 SYNC Signal
          3. 7.3.6.1.3 JESD204B/C Frame Assembly
          4. 7.3.6.1.4 JESD204B/C Frame Assembly in Bypass Mode
          5. 7.3.6.1.5 JESD204B/C Frame Assembly With Real Decimation
          6. 7.3.6.1.6 JESD204B,C Frame Assembly With Complex Decimation
        2. 7.3.6.2 JESD Output Reference Clock
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device Operating Mode Comparison
    5. 7.5 Programming
      1. 7.5.1 GPIO Control
      2. 7.5.2 SPI Register Write
      3. 7.5.3 SPI Register Read
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application: Spectrum Analyzer
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Input Signal Path: Wideband Receiver
        2. 8.2.1.2 Clocking
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Sampling Clock Requirements
      3. 8.2.3 Application Performance Plots
    3. 8.3 Typical Application: Time Domain Digitizer
      1. 8.3.1 Design Requirements
        1. 8.3.1.1 Input Signal Path: Time Domain Digitizer
      2. 8.3.2 Application Performance Plots
    4. 8.4 Initialization Set Up
    5. 8.5 Power Supply Recommendations
    6. 8.6 Layout
      1. 8.6.1 Layout Guidelines
      2. 8.6.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
      2. 9.1.2 Third-Party Products Disclaimer
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
7.3.6.1.5 JESD204B/C Frame Assembly With Real Decimation

Table 7-21 lists the available JESD204B/C interface configurations and corresponding SerDes lane rates. The boundary conditions are:

  • JESD204B: lane rates from 4 (min) to 15Gbps (max)
  • JESD204C: lane rates from 4 (min) to 24.75Gbps (max)

Examples of JESD204B/C frame assemblies are illustrated in Table 7-21 to Table 7-23.

Table 7-21 JESD Mode Options: Real Decimation
Output
Resolution
(bit)		LMFSJESD204B:
Lane Rate (Gbps)		JESD204B:
RATIO
[fSERDES/(FS/N)]		JESD204C:
Lane Rate (Gbps)		JESD204C:
RATIO
[fSERDES/(FS/N)]
164211FS x 20 x M / D / L10FS x 16 x 66 / 64 x M / D / L8.25
22212016.5
12414033
2111108.25
11212016.5
242231FS x 30 x M / D / L30FS x 24 x 66 / 64 x M / D / L24.75
12616049.5
11313024.75

D: Decimation setting

Table 7-22 Example JESD Frame Assembly: Real Decimation 16-bit output - Dual and Single Band
OUTPUT
LANE		LMFS =
4-2-1-1		LMFS =
2-2-2-1		LMFS =
1-2-4-1		LMFS =
2-1-1-1		LMFS =
1-1-2-1
STX0A0 [15:8]A0 [15:0]A0 [15:0]B0 [15:0]A0 [15:8]A0 [15:0]
STX1A0 [7:0]B0 [15:0]A0 [7:0]
STX2B0 [15:8]
STX3B0 [7:0]
STX4..7
Table 7-23 Example JESD Sample Frame Assembly: Real Decimation 24-bit output - Dual and Single Band
OUTPUT
LANE		LMFS =
2-2-3-1		LMFS =
1-2-6-1		LMFS =
1-1-3-1
STX0A0 [23:0]A0 [23:0]B0 [23:0]A0 [23:0]
STX1B0 [23:0]
STX2..7