SBASAL2 November   2025 ADC32RF72

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics - Power Consumption
    6. 5.6 Electrical Characteristics - DC Specifications
    7. 5.7 Electrical Characteristics - AC Specifications
    8. 5.8 Timing Requirements
    9. 5.9 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Inputs
        1. 7.3.1.1 Input Bandwidth
        2. 7.3.1.2 Background Calibration
      2. 7.3.2 ADC Channel Selection and Power Down Modes
      3. 7.3.3 Sampling Clock Input
      4. 7.3.4 SYSREF
        1. 7.3.4.1 SYSREF Monitor
      5. 7.3.5 Digital Signal Processor (DSP) Features
        1. 7.3.5.1 DSP Input Mux
        2. 7.3.5.2 Fractional Delay
        3. 7.3.5.3 Programmable FIR Filter for Equalization
        4. 7.3.5.4 DSP Output Mux
        5. 7.3.5.5 Digital Down Converter (DDC)
          1. 7.3.5.5.1 Decimation Filter Input
          2. 7.3.5.5.2 Decimation Modes
          3. 7.3.5.5.3 Decimation Filter Response
          4. 7.3.5.5.4 Numerically Controlled Oscillator (NCO)
            1. 7.3.5.5.4.1 NCO Update
            2. 7.3.5.5.4.2 NCO RESET
      6. 7.3.6 Digital Output Interface
        1. 7.3.6.1 JESD204B/C Interface
          1. 7.3.6.1.1 JESD204B Initial Lane Alignment (ILA)
          2. 7.3.6.1.2 SYNC Signal
          3. 7.3.6.1.3 JESD204B/C Frame Assembly
          4. 7.3.6.1.4 JESD204B/C Frame Assembly in Bypass Mode
          5. 7.3.6.1.5 JESD204B/C Frame Assembly With Real Decimation
          6. 7.3.6.1.6 JESD204B,C Frame Assembly With Complex Decimation
        2. 7.3.6.2 JESD Output Reference Clock
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device Operating Mode Comparison
    5. 7.5 Programming
      1. 7.5.1 GPIO Control
      2. 7.5.2 SPI Register Write
      3. 7.5.3 SPI Register Read
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application: Spectrum Analyzer
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Input Signal Path: Wideband Receiver
        2. 8.2.1.2 Clocking
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Sampling Clock Requirements
      3. 8.2.3 Application Performance Plots
    3. 8.3 Typical Application: Time Domain Digitizer
      1. 8.3.1 Design Requirements
        1. 8.3.1.1 Input Signal Path: Time Domain Digitizer
      2. 8.3.2 Application Performance Plots
    4. 8.4 Initialization Set Up
    5. 8.5 Power Supply Recommendations
    6. 8.6 Layout
      1. 8.6.1 Layout Guidelines
      2. 8.6.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
      2. 9.1.2 Third-Party Products Disclaimer
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
7.3.5.5.2 Decimation Modes

There are 2 different decimation modes supported and all 8x DDCs must be configured to the same mode:

  • Real decimation: The real input is low pass filtered and the filter output is down sampled by the decimation factor (M). The output of the DDC block in this mode is a real signal and detailed DDC chain is shown in Figure 7-23.
  • Complex decimation with real input: The DDC is given a real input that is mixed with an NCO to produce a complex output. The complex output is low pass filtered and down sampled by the decimation factor (M). The output of the DDC block in this mode is a complex signal and detailed DDC chain is shown in Figure 7-25.

Each DDC has an enable control signal. If the DDC is disabled, the output is zero. The following blocks are part of the DDC signal chain:

  • Decimation: The possible decimation factors are B x 2N where the base factor B can be 1, 3 or 5 and N can be a maximum of 15 for B = 1, 5 for B = 3 and 4 for B = 5.

    When the base factor is 3 or 5, all the DDCs must share the same decimation factor setting. However, when the base factor is 1 (decimations factors that are powers of 2), having an independent decimation factors per DDC is possible since each DDC has a samples repeater block. When each DDC is configured to a different decimation factor, the samples repeater for each DDC is adjusted so that all the DDC outputs are rate matched to highest data rate DDC. For example, if two DDCs are active and one is configured in decimation by 4 and the other in decimation by 16, the DDC configured for decimation by 16 automatically gets rate matched to the decimation by 4 rate by repeating the samples by a factor of 4. Upon successful configuration, the repeat factor can be readback for each DDC.

    Note: Independent decimation factors are not supported when any DDC is configured for decimation by 2. When decimation by 2 is used all other DDCs must be also be set to by 2.

    Repeat Factor: The repeat factor is adjusted automatically for each DDC in cases where the effective JESD line rate is below the lower threshold of 4Gbps. The repeat factor block is not available with base factors of 3 and 5.
  • DDC_PFIR: The ADC32RF72 has an integrated programmable FIR filter block in the decimation chain where the last stage filter is completely programmable. This feature is only available with decimation factors that are powers of 2 (B = 1). The block is referred to as the DDC_PFIR. Each DDC_PFIR has up to 96 total taps (across both inputs in complex decimation) with 17-bit resolution.
  • DDC coarse gain (G): The fixed digital gain can be applied to each DDC path where the gain G is an element of {0dB, 3dB, 6dB} and controllable for each DDC through the ddc_coarse_gain[7:0] signal.
  • DDC_EQ: The DDC_EQ supports all the same modes the as the Digital DSP EQ.
    Note: This EQ is not available for decimation factors of 2 and 3.
  • DDC_COMPLEX_GAIN: Each DDC has a programmable complex gain. In real decimation mode, only the real part of the gain is applied. The gain is in steps of 0.1dB from 0dB to 6dB; an independent gain setting is available for the real and imaginary parts.
ADC32RF72 Real Decimation Signal Chain (decimation factors that are powers of 2 (B = 1))Figure 7-23 Real Decimation Signal Chain (decimation factors that are powers of 2 (B = 1))
ADC32RF72 Real Decimation Signal Chain (decimation factors of 3 and 5 (B = 3, 5)Figure 7-24 Real Decimation Signal Chain (decimation factors of 3 and 5 (B = 3, 5)
ADC32RF72 Complex Decimation Signal Chain (decimation factors of 2 (B = 1)Figure 7-25 Complex Decimation Signal Chain (decimation factors of 2 (B = 1)
ADC32RF72 Complex Decimation Signal Chain (decimation factors of 3 and 5 (B = 3, 5)Figure 7-26 Complex Decimation Signal Chain (decimation factors of 3 and 5 (B = 3, 5)

The following parameters can be programmed:

Table 7-14 Input Selection to the DDC Programming
Function NameSizeDefaultAccessDescription
DDC{0..7}_DECIMATION_FACTOR_LSB81R/W

Set bits[15:0] of the 16-bit decimation factor for the DDC. Possible decimation factors are:

[2, 3, 4, 5, 6, 8, 10, 12, 16, 20, 24, 32, 40, 48, 64, 80, 96, 128, 256, 512, 1024, 2048, 4096, 8192, 16384, 32768]

DDC{0..7}_DECIMATION_FACTOR_MSB80R/W
DDC{0..7}_REPEAT_FACTOR_LSB81RBits[13:0] of the 14-bit repeat factor for the DDC.
DDC{0..7}_REPEAT_FACTOR_MSB60R
DDC{0..7}_PFIR_EN10R/W

Control the DDC_PFIR enable.

0: DDC_PFIR is disabled and a fixed decimation filter is used as the last stage filter.

1: DDC_PFIR is enabled and a programmable decimation filter is used as the last stage filter.

DDC{0..7}_PFIR_MODE_SEL10R/W

Select the DDC_PFIR mode.

0: Single channel mode.

1: Dual channel mode.

DDC{0..7}_PFIR_NUM_TAPS70R/W

Number of taps to be used by DDC_PFIR in a given mode. Can be any value when in single channel mode. Has to be even in dual channel mode.

1...96: Number of taps to be used by the DDC_PFIR.

DDC{0..7}_PFIR_TAPS30720R/W

Set the 96 taps of the DDC_PFIR block. Only 17 bits are written.

Single channel mode: Up to 96 taps are applied to ddc_pfir_input[0].

Dual channel mode: Up to 48 taps per ddc_pfir_input. First 48 taps apply to ddc_pfir_input[0]. Second 48 taps apply to ddc_pfir_input[1].

DDC{0..7}_EQ_EN10R/W

Control the DDC_EQ enable.

0: DDC_EQ is disabled and bypassed.

1: DDC_EQ is enabled and the DDC_EQ filter is applied to the DDC output.

DDC{0..7}_EQ_MODE_SEL30R/W

Select the DDC_EQ mode.

0: Single channel mode.

1: Dual channel mode.

2: Half complex mode.

3: Full complex mode.

4: Delay only mode.

DDC{0..7}_EQ_DEL_VAL70R/W

DDC_EQ delay value. The effect of this setting is dependent on the DDC_EQ mode.

0...127: Number of device clock cycles delay that is applied when DDC_EQ is in a mode with a programmable delay.

DDC{0..7}_EQ_NUM_TAPS70R/W

Number of taps to be used by DDC_EQ in a given mode. Can be any value when in single channel mode. Has to be even in dual channel mode and half complex mode. Has to be divisible by four in full complex mode.

1...96: Number of taps to be used by DDC_EQ.

DDC{0..7}_EQ_TAPS15360R/W

Set the 96 taps of the DDC_EQ block.

Single channel mode: Up to 96 taps are applied to ddc_eq_input[0].

Dual channel mode: Up to 48 taps per ddc_eq_input. First 48 taps apply to ddc_eq_input[0]. Second 48 taps apply to ddc_eq_input[1].

Half complex mode: Up to 48 taps per ddc_eq_input. First 48 taps apply to ddc_eq_input[0]. Second 48 taps apply to ddc_eq_input[1].

Full complex mode: Up to 48 taps per ddc_eq_input. First 48 taps apply to ddc_eq_input[0]; the first 24 of those taps apply to ddc_eq_output[0]. Second 48 taps apply to ddc_eq_input[1]; the first 24 of those taps apply to ddc_eq_output[0].

DDC{0..7}_COARSE_GAIN30R/W

Set a fixed digital gain in the DDC data path before the DDC_EQ.

0: 0dB digital gain.

3: 3dB digital gain.

6: 6dB digital gain (useful when using complex decimation).

DDC{0..7}_REAL_GAIN60R/W

Real part of the complex gain applied to the DDC output. The gain is in 0.1dB steps starting from to 0dB to 6dB.

0..60: Effective gain is DDC_REAL_GAIN*0.1dB

DDC{0..7}_IMAG_GAIN60R/W

Imaginary part of the complex gain applied to the DDC output (used in complex decimation modes). The gain is in 0.1dB steps starting from to 0dB to 6dB.

0..60: Effective imaginary gain is DDC_IMAG_GAIN*0.1dB