SBASAL2 November   2025 ADC32RF72

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics - Power Consumption
    6. 5.6 Electrical Characteristics - DC Specifications
    7. 5.7 Electrical Characteristics - AC Specifications
    8. 5.8 Timing Requirements
    9. 5.9 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Inputs
        1. 7.3.1.1 Input Bandwidth
        2. 7.3.1.2 Background Calibration
      2. 7.3.2 ADC Channel Selection and Power Down Modes
      3. 7.3.3 Sampling Clock Input
      4. 7.3.4 SYSREF
        1. 7.3.4.1 SYSREF Monitor
      5. 7.3.5 Digital Signal Processor (DSP) Features
        1. 7.3.5.1 DSP Input Mux
        2. 7.3.5.2 Fractional Delay
        3. 7.3.5.3 Programmable FIR Filter for Equalization
        4. 7.3.5.4 DSP Output Mux
        5. 7.3.5.5 Digital Down Converter (DDC)
          1. 7.3.5.5.1 Decimation Filter Input
          2. 7.3.5.5.2 Decimation Modes
          3. 7.3.5.5.3 Decimation Filter Response
          4. 7.3.5.5.4 Numerically Controlled Oscillator (NCO)
            1. 7.3.5.5.4.1 NCO Update
            2. 7.3.5.5.4.2 NCO RESET
      6. 7.3.6 Digital Output Interface
        1. 7.3.6.1 JESD204B/C Interface
          1. 7.3.6.1.1 JESD204B Initial Lane Alignment (ILA)
          2. 7.3.6.1.2 SYNC Signal
          3. 7.3.6.1.3 JESD204B/C Frame Assembly
          4. 7.3.6.1.4 JESD204B/C Frame Assembly in Bypass Mode
          5. 7.3.6.1.5 JESD204B/C Frame Assembly With Real Decimation
          6. 7.3.6.1.6 JESD204B,C Frame Assembly With Complex Decimation
        2. 7.3.6.2 JESD Output Reference Clock
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device Operating Mode Comparison
    5. 7.5 Programming
      1. 7.5.1 GPIO Control
      2. 7.5.2 SPI Register Write
      3. 7.5.3 SPI Register Read
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application: Spectrum Analyzer
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Input Signal Path: Wideband Receiver
        2. 8.2.1.2 Clocking
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Sampling Clock Requirements
      3. 8.2.3 Application Performance Plots
    3. 8.3 Typical Application: Time Domain Digitizer
      1. 8.3.1 Design Requirements
        1. 8.3.1.1 Input Signal Path: Time Domain Digitizer
      2. 8.3.2 Application Performance Plots
    4. 8.4 Initialization Set Up
    5. 8.5 Power Supply Recommendations
    6. 8.6 Layout
      1. 8.6.1 Layout Guidelines
      2. 8.6.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
      2. 9.1.2 Third-Party Products Disclaimer
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

5.7 Electrical Characteristics - AC Specifications

Maximum and minimum values are specified over the operating free-air temperature range and nominal supply voltages. Typical values are specified at TA = 25°C, ADC sampling rate = 1.5 GSPS, 100Ω termination, DDC Bypass mode, 50% clock duty cycle, nominal supply voltages and –1-dBFS differential input, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN(2) TYP MAX UNIT
AC ACCURACY
NSDflat Noise Spectral Density fIN = 600MHz, AIN = -20dBFS –163.7 dBFS/Hz
NF Noise Figure (100Ω termination) fIN = 600MHz, AIN = -20dBFS 14.4 dB
SNR Signal to noise ratio fIN = 100MHz 73.0 dBFS
SNRflat(1) Signal to noise ratio measured from 100MHz to FS/2 within the Nyquist zone fIN = 100MHz 72.0 75.3 dBFS
fIN = 600MHz 73.4
fIN = 600MHz, AIN = -20dBFS 75.5
fIN = 900MHz 72.1
fIN = 1.4GHz 69.0
SINADflat(1) Signal to noise and distortion ratio fIN = 100MHz 74.3 dBFS
ENOB Effective number of bits fIN = 100MHz 11.8 Bits
THD Total Harmonic Distortion (First five harmonics) fIN = 100MHz 82 dBc
fIN = 600MHz 74
fIN = 900MHz 68
fIN = 1.4GHz 57
HD2 Second Harmonic Distortion fIN = 100MHz 74 88 dBc
fIN = 600MHz 77
fIN = 900MHz 74
fIN = 1.4GHz 64
HD3 Third Harmonic Distortion fIN = 100MHz 74 83 dBc
fIN = 600MHz 77
fIN = 900MHz 68
fIN = 1.4GHz 58
Non HD2,3 Spur free dynamic range (excluding HD2 and HD3) fIN = 100MHz 80 95 dBFS
fIN = 600MHz 90
fIN = 900MHz 93
fIN = 1.4GHz 79
IMD3 Two tone inter-modulation distortion f1 = 100MHz, f2 = 200MHz, AIN = -7dBFS/tone 89 dBFS
f1 = 0.9GHz, f2 = 1.0GHz, AIN = -7dBFS/tone 76
(1) For detailed description of SNRflat and NSDflat see Section 6.
(2) SNRflat, HD3 and Non HD23 minimum values are specified by final test; HD2 is specified by bench characterization.