SBASAL2 November   2025 ADC32RF72

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics - Power Consumption
    6. 5.6 Electrical Characteristics - DC Specifications
    7. 5.7 Electrical Characteristics - AC Specifications
    8. 5.8 Timing Requirements
    9. 5.9 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Inputs
        1. 7.3.1.1 Input Bandwidth
        2. 7.3.1.2 Background Calibration
      2. 7.3.2 ADC Channel Selection and Power Down Modes
      3. 7.3.3 Sampling Clock Input
      4. 7.3.4 SYSREF
        1. 7.3.4.1 SYSREF Monitor
      5. 7.3.5 Digital Signal Processor (DSP) Features
        1. 7.3.5.1 DSP Input Mux
        2. 7.3.5.2 Fractional Delay
        3. 7.3.5.3 Programmable FIR Filter for Equalization
        4. 7.3.5.4 DSP Output Mux
        5. 7.3.5.5 Digital Down Converter (DDC)
          1. 7.3.5.5.1 Decimation Filter Input
          2. 7.3.5.5.2 Decimation Modes
          3. 7.3.5.5.3 Decimation Filter Response
          4. 7.3.5.5.4 Numerically Controlled Oscillator (NCO)
            1. 7.3.5.5.4.1 NCO Update
            2. 7.3.5.5.4.2 NCO RESET
      6. 7.3.6 Digital Output Interface
        1. 7.3.6.1 JESD204B/C Interface
          1. 7.3.6.1.1 JESD204B Initial Lane Alignment (ILA)
          2. 7.3.6.1.2 SYNC Signal
          3. 7.3.6.1.3 JESD204B/C Frame Assembly
          4. 7.3.6.1.4 JESD204B/C Frame Assembly in Bypass Mode
          5. 7.3.6.1.5 JESD204B/C Frame Assembly With Real Decimation
          6. 7.3.6.1.6 JESD204B,C Frame Assembly With Complex Decimation
        2. 7.3.6.2 JESD Output Reference Clock
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device Operating Mode Comparison
    5. 7.5 Programming
      1. 7.5.1 GPIO Control
      2. 7.5.2 SPI Register Write
      3. 7.5.3 SPI Register Read
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application: Spectrum Analyzer
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Input Signal Path: Wideband Receiver
        2. 8.2.1.2 Clocking
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Sampling Clock Requirements
      3. 8.2.3 Application Performance Plots
    3. 8.3 Typical Application: Time Domain Digitizer
      1. 8.3.1 Design Requirements
        1. 8.3.1.1 Input Signal Path: Time Domain Digitizer
      2. 8.3.2 Application Performance Plots
    4. 8.4 Initialization Set Up
    5. 8.5 Power Supply Recommendations
    6. 8.6 Layout
      1. 8.6.1 Layout Guidelines
      2. 8.6.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
      2. 9.1.2 Third-Party Products Disclaimer
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

5.6 Electrical Characteristics - DC Specifications

Maximum and minimum values are specified over the operating free-air temperature range and nominal supply voltages. Typical values are specified at TA = 25°C, ADC sampling rate = 1.5 GSPS, DDC Bypass mode, 50% clock duty cycle, nominal supply voltages and –1-dBFS differential input, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DC ACCURACY
No missing codes 16 bits
DNL Differential nonlinearity FIN = 10 MHz 0.3 LSB
INL Integral nonlinearity FIN = 10 MHz 2.5 LSB
VOS_ERR Offset error 0.9 %FSR
GAINERR Gain error 1.0 %FSR
GAINMatching Gain matching across channels 0.1 dB
ADC ANALOG INPUTS (IN0P/N, IN1P/N, IN2P/N, IN3P/N)
FS Input full scale Differential 1.4375 Vpp
VICM Input common model voltage 1.25 1.35 1.45 V
ZIN Differential input impedance Differential at 100 MHz 100 Ω
VOCM Output common mode voltage 1.35 V
BW Analog Input Bandwidth (-3dB) 1.8 GHz
CMRR Common mode rejection ratio FIN = 100 MHz 30 dB
CLOCK INPUT (CLKP/N)
Input clock frequency 500 1500 MHz
VID Differential input voltage 0.6 2.0 2.8 Vpp
VICM Input common mode voltage 0.7 V
ZIN Differential input impedance Differential at 1.5 GHz 100 Ω
Clock duty cycle 30 50 70 %
SYSREF INPUT (SYSREFP/N)
VID Differential input voltage 350 450 800 mVpp
VICM Input common mode voltage 1.05 1.2 1.325 V
Digital Inputs (GPIO1..23, RESET, SCLK, SEN, SDIO, SYNC)
VIH High level input voltage 1.15 V
VIL Low level input voltage 0.65 V
IIH High level input current -250 250 μA
IIL Low level input current -250 250 μA
CI Input capacitance 2 pF
DIGITAL OUTPUT (SDIO, SDOUT)
VOH High level output voltage ILOAD = -400 μA AVDDGPIO18– 0.1 AVDDGPIO18 V
VOL Low level output voltage ILOAD = 400 μA 0.1 V
CML SERDES OUTPUTS: STX[0..7]P/N
VOD SerDes transmitter output amplitude differential peak-peak 950 mVpp
VOCM SerDes transmitter output common mode 450 mV
ZTX SerDes transmitter single ended termination impedance 50 Ω
Transmitter short-circuit current Transmitter pins shorted to any voltage between –0.25 V and 1.45 V –100 100 mA