SBASAL2 November   2025 ADC32RF72

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics - Power Consumption
    6. 5.6 Electrical Characteristics - DC Specifications
    7. 5.7 Electrical Characteristics - AC Specifications
    8. 5.8 Timing Requirements
    9. 5.9 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Inputs
        1. 7.3.1.1 Input Bandwidth
        2. 7.3.1.2 Background Calibration
      2. 7.3.2 ADC Channel Selection and Power Down Modes
      3. 7.3.3 Sampling Clock Input
      4. 7.3.4 SYSREF
        1. 7.3.4.1 SYSREF Monitor
      5. 7.3.5 Digital Signal Processor (DSP) Features
        1. 7.3.5.1 DSP Input Mux
        2. 7.3.5.2 Fractional Delay
        3. 7.3.5.3 Programmable FIR Filter for Equalization
        4. 7.3.5.4 DSP Output Mux
        5. 7.3.5.5 Digital Down Converter (DDC)
          1. 7.3.5.5.1 Decimation Filter Input
          2. 7.3.5.5.2 Decimation Modes
          3. 7.3.5.5.3 Decimation Filter Response
          4. 7.3.5.5.4 Numerically Controlled Oscillator (NCO)
            1. 7.3.5.5.4.1 NCO Update
            2. 7.3.5.5.4.2 NCO RESET
      6. 7.3.6 Digital Output Interface
        1. 7.3.6.1 JESD204B/C Interface
          1. 7.3.6.1.1 JESD204B Initial Lane Alignment (ILA)
          2. 7.3.6.1.2 SYNC Signal
          3. 7.3.6.1.3 JESD204B/C Frame Assembly
          4. 7.3.6.1.4 JESD204B/C Frame Assembly in Bypass Mode
          5. 7.3.6.1.5 JESD204B/C Frame Assembly With Real Decimation
          6. 7.3.6.1.6 JESD204B,C Frame Assembly With Complex Decimation
        2. 7.3.6.2 JESD Output Reference Clock
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device Operating Mode Comparison
    5. 7.5 Programming
      1. 7.5.1 GPIO Control
      2. 7.5.2 SPI Register Write
      3. 7.5.3 SPI Register Read
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application: Spectrum Analyzer
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Input Signal Path: Wideband Receiver
        2. 8.2.1.2 Clocking
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Sampling Clock Requirements
      3. 8.2.3 Application Performance Plots
    3. 8.3 Typical Application: Time Domain Digitizer
      1. 8.3.1 Design Requirements
        1. 8.3.1.1 Input Signal Path: Time Domain Digitizer
      2. 8.3.2 Application Performance Plots
    4. 8.4 Initialization Set Up
    5. 8.5 Power Supply Recommendations
    6. 8.6 Layout
      1. 8.6.1 Layout Guidelines
      2. 8.6.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
      2. 9.1.2 Third-Party Products Disclaimer
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

7.3.2 ADC Channel Selection and Power Down Modes

There are 4 different ADC channels (Ch0...3) available however channel 0 always has to be enabled. The user can select any of the remaining 3 via the channel enable control shown below in the system parameters. This is a static configuration that needs to be set at power up.

The device supports three different power down modes that can be controlled via GPIO pins or SPI register writes:

  • Fast Power Down: individual channel power down with shorter wake up time but higher power consumption. JESD interface stays active.
  • Power Down: individual channel power down. JESD interface can be adjusted and power down unused lanes.
  • Global Power Down: power down of entire chip for lowest power consumption (enabled via function call).
Table 7-2 Power Down Modes Comparison
Power Down ModeWake Up TimePower Consumption (typ)Comment
Fast Power Down~ 5 us~ 2.0WJESD interface stays active
Global Power Downdepends on JESD interface~ 0.4WJESD interface powered down

The power down modes can be can be programmed using the following parameters:

Table 7-3 Power Down Modes Programming
System Parameter NameSizeDefaultAccessDescription
ADC_EN_BITMAP43R/WSelect two out of the 4 ADCs.

3: Channel 0 and 1 are active.

5: Channel 0 and 2 are active.

9: Channel 0 and 3 are active.

ADC_CH_PDN_VAL40R/WIndividual ADC channel power down setting. Each ADC gets one bit. If the bit is set, the corresponding channel is powered down. ADC_CH_PDN_SRC_SEL needs to be set to 1 for this setting to take effect.

Bit 0: ADC0 power down control.

Bit 1: ADC1 power down control.

Bit 2: ADC2 power down control.

Bit 3: ADC3 power down control.

ADC_CH_PDN_SRC_SEL10R/WSelect if channel power down signal is coming from a GPIO or SPI.

0: Channel power down is from GPIO.

1: Channel power down is coming from ADC_CH_PDN_VAL.

ADC_CH_PDN_MODE10R/WSelect the channel power down mode.

0: Normal PDN (least power consumption for each channel).

1: Fast PDN (faster power up time but higher power consumption).