SBASAL2 November   2025 ADC32RF72

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics - Power Consumption
    6. 5.6 Electrical Characteristics - DC Specifications
    7. 5.7 Electrical Characteristics - AC Specifications
    8. 5.8 Timing Requirements
    9. 5.9 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Inputs
        1. 7.3.1.1 Input Bandwidth
        2. 7.3.1.2 Background Calibration
      2. 7.3.2 ADC Channel Selection and Power Down Modes
      3. 7.3.3 Sampling Clock Input
      4. 7.3.4 SYSREF
        1. 7.3.4.1 SYSREF Monitor
      5. 7.3.5 Digital Signal Processor (DSP) Features
        1. 7.3.5.1 DSP Input Mux
        2. 7.3.5.2 Fractional Delay
        3. 7.3.5.3 Programmable FIR Filter for Equalization
        4. 7.3.5.4 DSP Output Mux
        5. 7.3.5.5 Digital Down Converter (DDC)
          1. 7.3.5.5.1 Decimation Filter Input
          2. 7.3.5.5.2 Decimation Modes
          3. 7.3.5.5.3 Decimation Filter Response
          4. 7.3.5.5.4 Numerically Controlled Oscillator (NCO)
            1. 7.3.5.5.4.1 NCO Update
            2. 7.3.5.5.4.2 NCO RESET
      6. 7.3.6 Digital Output Interface
        1. 7.3.6.1 JESD204B/C Interface
          1. 7.3.6.1.1 JESD204B Initial Lane Alignment (ILA)
          2. 7.3.6.1.2 SYNC Signal
          3. 7.3.6.1.3 JESD204B/C Frame Assembly
          4. 7.3.6.1.4 JESD204B/C Frame Assembly in Bypass Mode
          5. 7.3.6.1.5 JESD204B/C Frame Assembly With Real Decimation
          6. 7.3.6.1.6 JESD204B,C Frame Assembly With Complex Decimation
        2. 7.3.6.2 JESD Output Reference Clock
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device Operating Mode Comparison
    5. 7.5 Programming
      1. 7.5.1 GPIO Control
      2. 7.5.2 SPI Register Write
      3. 7.5.3 SPI Register Read
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application: Spectrum Analyzer
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Input Signal Path: Wideband Receiver
        2. 8.2.1.2 Clocking
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Sampling Clock Requirements
      3. 8.2.3 Application Performance Plots
    3. 8.3 Typical Application: Time Domain Digitizer
      1. 8.3.1 Design Requirements
        1. 8.3.1.1 Input Signal Path: Time Domain Digitizer
      2. 8.3.2 Application Performance Plots
    4. 8.4 Initialization Set Up
    5. 8.5 Power Supply Recommendations
    6. 8.6 Layout
      1. 8.6.1 Layout Guidelines
      2. 8.6.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
      2. 9.1.2 Third-Party Products Disclaimer
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

7.3.5.2 Fractional Delay

The device includes an optional programmable 12-bit fractional digital delay after the DSP input mux (see Figure 7-13). There are two independent digital fractional delay blocks - FDF0 and FDF1. Each FDF block is connected to two input streams (dsp_in[1:0] or dsp_in[3:2]) where each input stream has a programmable fractional delay value, td00 and td01 for dsp_in[1:0] and td10 and td11 for dsp_in[3:2]. The FDF blocks output a total of four data streams (fdf_out[3:0]) where each output stream corresponds to a distinct fractionally delayed input stream.

The fractional delay is a true time delay implementation with a linear phase across frequencies. The fractional delay calculates to:

Fractional Delay [sampling clock period] = Delay / 4096x TS (sampling period).

ADC32RF72 Fractional Delay FeatureFigure 7-13 Fractional Delay Feature

As an example, a setting of 2048 equals ½ a clock cycle delay as shown in Figure 7-14. The magnitude error is less than −80dB (vs desired delay).

ADC32RF72 Fractional delay = ½ clock cycle (delay setting = 2048)Figure 7-14 Fractional delay = ½ clock cycle
(delay setting = 2048)
ADC32RF72 Error magnitude(desired vs actual waveform)Figure 7-15 Error magnitude
(desired vs actual waveform)

The fractional delay is configured via SPI register writes and the programmed delay is internally translated into filter coefficients. The filter response is shown in Figure 7-16 and Figure 7-17. The passband is approximately 85% of the Nyquist zone. Reprogramming the fractional delay can take up to 2µs to update the filter coefficients.

ADC32RF72 Filter response of the fractional delay FIRFigure 7-16 Filter response of the fractional delay FIR
ADC32RF72 Filter response of the fractional delay FIR (zoom)Figure 7-17 Filter response of the fractional delay FIR (zoom)

The fractional delay can be can be programmed using the following parameters:

Table 7-9 Fractional Delay Configuration Programming

System Parameter Name

SizeDefaultAccessDescription
FDF0_DELAY_VAL_0_LSB80R/WBits [7:0] of the fractional delay value for 0th input data stream to FDF0.
FDF0_DELAY_VAL_0_MSB40R/WBits [11:8] of the fractional delay value for 0th input data stream to FDF0.
FDF0_DELAY_VAL_1_LSB80R/WBits [7:0] of the fractional delay value for 1st input data stream to FDF0.
FDF0_DELAY_VAL_1_MSB40R/WBits [11:8] of the fractional delay value for 1st input data stream to FDF0.
FDF1_DELAY_VAL_0_LSB80R/WBits [7:0] of the fractional delay value for 0th input data stream to FDF1.
FDF1_DELAY_VAL_0_MSB40R/WBits [11:8] of the fractional delay value for 0th input data stream to FDF1.
FDF1_DELAY_VAL_1_LSB80R/WBits [7:0] of the fractional delay value for 1st input data stream to FDF1.
FDF1_DELAY_VAL_1_MSB40R/WBits [11:8] of the fractional delay value for 1st input data stream to FDF1.