SBASAL2 November   2025 ADC32RF72

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics - Power Consumption
    6. 5.6 Electrical Characteristics - DC Specifications
    7. 5.7 Electrical Characteristics - AC Specifications
    8. 5.8 Timing Requirements
    9. 5.9 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Inputs
        1. 7.3.1.1 Input Bandwidth
        2. 7.3.1.2 Background Calibration
      2. 7.3.2 ADC Channel Selection and Power Down Modes
      3. 7.3.3 Sampling Clock Input
      4. 7.3.4 SYSREF
        1. 7.3.4.1 SYSREF Monitor
      5. 7.3.5 Digital Signal Processor (DSP) Features
        1. 7.3.5.1 DSP Input Mux
        2. 7.3.5.2 Fractional Delay
        3. 7.3.5.3 Programmable FIR Filter for Equalization
        4. 7.3.5.4 DSP Output Mux
        5. 7.3.5.5 Digital Down Converter (DDC)
          1. 7.3.5.5.1 Decimation Filter Input
          2. 7.3.5.5.2 Decimation Modes
          3. 7.3.5.5.3 Decimation Filter Response
          4. 7.3.5.5.4 Numerically Controlled Oscillator (NCO)
            1. 7.3.5.5.4.1 NCO Update
            2. 7.3.5.5.4.2 NCO RESET
      6. 7.3.6 Digital Output Interface
        1. 7.3.6.1 JESD204B/C Interface
          1. 7.3.6.1.1 JESD204B Initial Lane Alignment (ILA)
          2. 7.3.6.1.2 SYNC Signal
          3. 7.3.6.1.3 JESD204B/C Frame Assembly
          4. 7.3.6.1.4 JESD204B/C Frame Assembly in Bypass Mode
          5. 7.3.6.1.5 JESD204B/C Frame Assembly With Real Decimation
          6. 7.3.6.1.6 JESD204B,C Frame Assembly With Complex Decimation
        2. 7.3.6.2 JESD Output Reference Clock
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device Operating Mode Comparison
    5. 7.5 Programming
      1. 7.5.1 GPIO Control
      2. 7.5.2 SPI Register Write
      3. 7.5.3 SPI Register Read
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application: Spectrum Analyzer
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Input Signal Path: Wideband Receiver
        2. 8.2.1.2 Clocking
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Sampling Clock Requirements
      3. 8.2.3 Application Performance Plots
    3. 8.3 Typical Application: Time Domain Digitizer
      1. 8.3.1 Design Requirements
        1. 8.3.1.1 Input Signal Path: Time Domain Digitizer
      2. 8.3.2 Application Performance Plots
    4. 8.4 Initialization Set Up
    5. 8.5 Power Supply Recommendations
    6. 8.6 Layout
      1. 8.6.1 Layout Guidelines
      2. 8.6.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
      2. 9.1.2 Third-Party Products Disclaimer
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

7.3.5.3 Programmable FIR Filter for Equalization

The ADC32RF7x includes an integrated programmable FIR filter block referred to as an equalizer (EQ). As illustrated in Figure 7-18, there are two EQ blocks (EQ0 and EQ1) which are located at the output of the fractional delay filters (FDF0/1). Each EQ block can source the input data stream from either dsp_in directly or from the preceding FDF block. There are a total of four output data streams (eq_out[3:0]) where each output stream corresponds to a distinct filtered input stream.

Each of the two equalizers (EQ0/EQ1) include up to 192-taps (16-bit) shared across two input streams.

ADC32RF72 FIR Equalizer ConfigurationsFigure 7-18 FIR Equalizer Configurations

Each EQ supports several different configurations with up to 192-taps per EQFIR as shown in Figure 7-19.

ADC32RF72 FIR Equalizer Configurations for EQ0 (x=0) and EQ1 (x=1)Figure 7-19 FIR Equalizer Configurations for EQ0 (x=0) and EQ1 (x=1)

The power consumption scales linearly with sampling rate and with # of taps used. Unused taps can be set to 0.

The digital equalizer can be can be programmed using the following parameters:

Table 7-10 EQ{x} Configuration Programming (x= 0,1)

System Parameter Name

SizeDefaultAccessDescription
EQ{x}_IN_SRC_SEL10R/W

Select EQ{x} input data source.

0: EQ{x} input from DSP_IN[2x+1, 2x].

1: EQ{x} input from FDF_OUT[2x+1, 2x].

EQ{x}_MODE_SEL30R/W

Select EQ{x} mode.

0: Single channel mode.

1: Dual channel mode.

2: Half complex mode.

3: Full complex mode.

4: Delay only mode.

EQ{x}_DEL_VAL80R/W

EQ{x} delay value. The effect of this setting is dependent on the EQ{x} mode.

0...255: Number of device clock cycles delay that is applied when EQ{x} is in a mode with a programmable delay.

EQ{x}_NUM_TAPS80R/W

Number of taps to be used by EQ{x} in a given mode. Can be any value when in single channel mode. Has to be even in dual channel mode and half complex mode. Has to be divisible by four in full complex mode.

1...192: Number of taps to be used by EQ{x}.

EQ{x}_TAPS30720R/W

Set the 192 taps of the EQ{x} block.

Single channel mode: Up to 192 taps are applied to eq_input[2x].

Dual channel mode: Up to 96 taps per eq_input. First 96 taps apply to eq_input[2x]. Second 96 taps apply to eq_input[2x+1].

Half complex mode: Up to 96 taps per eq_input. First 96 taps apply to eq_input[2x]. Second 96 taps apply to eq_input[2x+1].

Full complex mode: Up to 96 taps per eq_input. First 96 taps apply to eq_input[2x]; the first 48 of those taps apply to eq_output[2x]. Second 96 taps apply to eq_input[2x+1]; the first 48 of those taps apply to eq_output[2x].