SBASAL2 November   2025 ADC32RF72

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics - Power Consumption
    6. 5.6 Electrical Characteristics - DC Specifications
    7. 5.7 Electrical Characteristics - AC Specifications
    8. 5.8 Timing Requirements
    9. 5.9 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Inputs
        1. 7.3.1.1 Input Bandwidth
        2. 7.3.1.2 Background Calibration
      2. 7.3.2 ADC Channel Selection and Power Down Modes
      3. 7.3.3 Sampling Clock Input
      4. 7.3.4 SYSREF
        1. 7.3.4.1 SYSREF Monitor
      5. 7.3.5 Digital Signal Processor (DSP) Features
        1. 7.3.5.1 DSP Input Mux
        2. 7.3.5.2 Fractional Delay
        3. 7.3.5.3 Programmable FIR Filter for Equalization
        4. 7.3.5.4 DSP Output Mux
        5. 7.3.5.5 Digital Down Converter (DDC)
          1. 7.3.5.5.1 Decimation Filter Input
          2. 7.3.5.5.2 Decimation Modes
          3. 7.3.5.5.3 Decimation Filter Response
          4. 7.3.5.5.4 Numerically Controlled Oscillator (NCO)
            1. 7.3.5.5.4.1 NCO Update
            2. 7.3.5.5.4.2 NCO RESET
      6. 7.3.6 Digital Output Interface
        1. 7.3.6.1 JESD204B/C Interface
          1. 7.3.6.1.1 JESD204B Initial Lane Alignment (ILA)
          2. 7.3.6.1.2 SYNC Signal
          3. 7.3.6.1.3 JESD204B/C Frame Assembly
          4. 7.3.6.1.4 JESD204B/C Frame Assembly in Bypass Mode
          5. 7.3.6.1.5 JESD204B/C Frame Assembly With Real Decimation
          6. 7.3.6.1.6 JESD204B,C Frame Assembly With Complex Decimation
        2. 7.3.6.2 JESD Output Reference Clock
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device Operating Mode Comparison
    5. 7.5 Programming
      1. 7.5.1 GPIO Control
      2. 7.5.2 SPI Register Write
      3. 7.5.3 SPI Register Read
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application: Spectrum Analyzer
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Input Signal Path: Wideband Receiver
        2. 8.2.1.2 Clocking
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Sampling Clock Requirements
      3. 8.2.3 Application Performance Plots
    3. 8.3 Typical Application: Time Domain Digitizer
      1. 8.3.1 Design Requirements
        1. 8.3.1.1 Input Signal Path: Time Domain Digitizer
      2. 8.3.2 Application Performance Plots
    4. 8.4 Initialization Set Up
    5. 8.5 Power Supply Recommendations
    6. 8.6 Layout
      1. 8.6.1 Layout Guidelines
      2. 8.6.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
      2. 9.1.2 Third-Party Products Disclaimer
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

4 Pin Configuration and Functions

ADC32RF72 289-Ball Flip Chip BGA (Top View) Figure 4-1 289-Ball Flip Chip BGA
(Top View)
Table 4-1 Pin Functions
PINTYPE(1)DESCRIPTION
NAMENO.
AVDD12B3,B4,B5,B6,B7,B8,B9,
B10,B11,B12,B13,B14,B15,F9,M3,M4,M8,M11,M14,
M15,N3,N4,N8,N11,N14,
N15,P3,P4,P8,P11,P14,
P15,R3,R4,R14,R15		PAnalog 1.2V supply. Low noise LDO recommended.
AVDDCLK12T9, T10, U12PClock power supply, 1.2V. Low noise LDO recommended
AVDD18E9,H5,H13,J13,M6,M13,
N1,N6,N13,N17,P6,P13,
R6,R13,T1,T3,T4,T14,T15,
T17		PAnalog 1.8V supply. Low noise LDO recommended
AVDDCLK18T8, T11PClock power supply, 1.8V. Low noise LDO recommended
AVDDGPIO18L5P1.8V power supply for GPIO pins.
CLKN,
CLKP		U9,
U10		IDifferential clock input. Internal differential 100Ω termination and self bias to common mode voltage of 0.7V. Must be AC coupled externally.
DVDD09C8, D8, E8, F8,G8, H8, J8,
K8, K13, L6,L7, L8,
L9, L10, L11, L12, L13		PDigital power supply, 0.9V. Switching DC/DC regulator is recommended.
GNDA1,A6,A9,A12,A17,B2,B16,
C10,D1,D10,D17,E10,F10,G5,G9,G10,G13,H9,H10,
J6,J7,J9,J10,J11,J12,K6,
K7,K9,K10,K11,K12,M1,
M2,M5,M7,M9, M10,M12,
M16,M17,N2,N5,N9,N10,
N12,N16,P2,P5,P9,P10,
P12,P16,R2,R5,R7,R8,
R9,R10,R11,R12,R16,T2,
T5,T6,T13,T16,U1,U2,
U5,U8,U11,U13,U16,U17		GGround, 0V
GPIO1,
GPIO2,
GPIO3		K4,
L14,
J15		I/OThe GPIO pins can be assigned different functions using SPI writes. See Section 7.5.1.
GPIO8,
GPIO9,
GPIO10		L4,
J3,
K3,		I/O
GPIO12 to GPIO23J2, K2, L2, C2,
D2, K16,L16, J17, K17,
L17, C16, D16		I/O
IN0N,
IN0P		R17,
P17		IDifferential analog input, ch 0. Internal programmable 50, 100 and 200Ω termination.
IN1N,
INIP		U14,
U15		IDifferential analog input, ch 1. Internal programmable 50, 100 and 200Ω termination.
IN2N,
IN2P		P1,
R1		IDifferential analog input, ch 2. Internal programmable 50, 100 and 200Ω termination.
IN3N,
IN3P		U3,
U4		IDifferential analog input, ch 3. Internal programmable 50, 100 and 200Ω termination.
JESDCLKN,
JESDCLKP		C9,
D9		ODifferential JESD output clock. LVDS logic levels. Can be configured to serdes lane rate divided by (8x k). By default this feature is powered down and pins can be left floating. This output clock is derived directly from the internal SerDes PLL and does not provide deterministic latency.
LVDSDCLK0N,
LVDSDCLK0P		F17,
E17		ODifferential LVDS bit clock output.
Not yet supported in software. Leave as 'No Connect'
LVDSDCLK1N,
LVDSDCLK1P		F1,
E1		O
LVDSFCLK0N,
LVDSFCLK0P		H17,
G17		ODifferential LVDS frame clock output.
Not yet supported in software. Leave as 'No Connect'
LVDSFCLK1N,
LVDSFCLK1P		H1,
G1		O
LVDSD0N,
LVDSD0P		G11,
H11		OLVDS output interface
Not yet supported in software. Leave as 'No Connect'
LVDSD1N,
LVDSD1P		E11,
F11		O
LVDSD2N,
LVDSD2P		C11,
D11		O
LVDSD3N,
LVDSD3P		G12,
H12		O
LVDSD4N,
LVDSD4P		E12,
F12		O
LVDSD5N,
LVDSD5P		C12,
D12		O
LVDSD6N,
LVDSD6P		E13,
F13		O
LVDSD7N,
LVDSD7P		C13,
D13		O
LVDSD8N,
LVDSD8P		G14,
H14		O
LVDSD9N,
LVDSD9P		E14,
F14		O
LVDSD10N,
LVDSD10P		C14,
D14		O
LVDSD11N,
LVDSD11P		G15,
H15		O
LVDSD12N,
LVDSD12P		E15,
F15		O
LVDSD13N,
LVDSD13P		C15,
D15		O
LVDSD14N,
LVDSD14P		G16,
H16		O
LVDSD15N,
LVDSD15P		E16,
F16		O
LVDSD16N,
LVDSD16P		G7,
H7		O
LVDSD17N,
LVDSD17P		E7,
F7		O
LVDSD18N,
LVDSD18P		C7,
D7		O
LVDSD19N,
LVDSD19P		G6,
H6		O
LVDSD20N,
LVDSD20P		E6,
F6		O
LVDSD21N,
LVDSD21P		C6,
D6		O
LVDSD22N,
LVDSD22P		E5,
F5		O
LVDSD23N,
LVDSD23P		C5,
D5		O
LVDSD24N,
LVDSD24P		G4,
H4		O
LVDSD25N,
LVDSD25P		E4,
F4		O
LVDSD26N,
LVDSD26P		C4,
D4		O
LVDSD27N,
LVDSD27P		G3,
H3		O
LVDSD28N,
LVDSD28P		E3,
F3		O
LVDSD29N,
LVDSD29P		C3,
D3		OLVDS output interface
Not yet supported in software. Leave as 'No Connect'
LVDSD30N,
LVDSD30P		G2,
H2		O
LVDSD31N,
LVDSD31P		E2,
F2		O
NCJ5,J14,K1,K5,K14,L1-Do not connect
RESETJ1IHardware reset. Active low. This pin has an internal 10kΩ pullup resistor to AVDD18.
SCLKK15ISerial interface clock input. This pin has an internal 10kΩ pulldown resistor.
SDIOL15I/OSerial interface data input/output. This pin has an internal 10kΩ pulldown resistor.
SDOUTL3OSerial interface data output.
SENJ16ISerial interface enable. Active low. This pin has an internal 10kΩ pullup resistor to AVDD18.
STX0N,
STX0P		C17,
B17		ODifferential, high-speed serial JESD204B/C output data interface, lane 0
STX1N,
STX1P		A16,
A15		ODifferential, high-speed serial JESD204B/C output data interface, lane 1
STX2N,
STX2P		A14,
A13		ODifferential, high-speed serial JESD204B/C output data interface, lane 2
STX3N,
STX3P		A11,
A10		ODifferential, high-speed serial JESD204B/C output data interface, lane 3
STX4N,
STX4P		C1,
B1		ODifferential, high-speed serial JESD204B/C output data interface, lane 4
STX5N,
STX5P		A2,
A3		ODifferential, high-speed serial JESD204B/C output data interface, lane 5
STX6N,
STX6P		A4,
A5		ODifferential, high-speed serial JESD204B/C output data interface, lane 6
STX7N,
STX7P		A7,
A8		ODifferential, high-speed serial JESD204B/C output data interface, lane 7
SYNCJ4IJESD active low SYNC input. When SYNC is low and the device is configured, the device sends K characters on the JESD lanes.
SYSREFN,
SYSREFP		U6,
U7		IDifferential SYSREF input (100Ω differential termination, self biased to 1.2V). AC and DC coupling is supported.
TIMESTAMPN,
TIMESTAMPP		P7,
N7		INot yet supported in software. Can be connected to GND.
VCMT7, T12OCommon mode voltage reference output. The two pins are internally shorted together.
(1) I = Input, O = Output, I/O = Input or Output, G = Ground, P = Power.