SBASAL2 November   2025 ADC32RF72

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics - Power Consumption
    6. 5.6 Electrical Characteristics - DC Specifications
    7. 5.7 Electrical Characteristics - AC Specifications
    8. 5.8 Timing Requirements
    9. 5.9 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Inputs
        1. 7.3.1.1 Input Bandwidth
        2. 7.3.1.2 Background Calibration
      2. 7.3.2 ADC Channel Selection and Power Down Modes
      3. 7.3.3 Sampling Clock Input
      4. 7.3.4 SYSREF
        1. 7.3.4.1 SYSREF Monitor
      5. 7.3.5 Digital Signal Processor (DSP) Features
        1. 7.3.5.1 DSP Input Mux
        2. 7.3.5.2 Fractional Delay
        3. 7.3.5.3 Programmable FIR Filter for Equalization
        4. 7.3.5.4 DSP Output Mux
        5. 7.3.5.5 Digital Down Converter (DDC)
          1. 7.3.5.5.1 Decimation Filter Input
          2. 7.3.5.5.2 Decimation Modes
          3. 7.3.5.5.3 Decimation Filter Response
          4. 7.3.5.5.4 Numerically Controlled Oscillator (NCO)
            1. 7.3.5.5.4.1 NCO Update
            2. 7.3.5.5.4.2 NCO RESET
      6. 7.3.6 Digital Output Interface
        1. 7.3.6.1 JESD204B/C Interface
          1. 7.3.6.1.1 JESD204B Initial Lane Alignment (ILA)
          2. 7.3.6.1.2 SYNC Signal
          3. 7.3.6.1.3 JESD204B/C Frame Assembly
          4. 7.3.6.1.4 JESD204B/C Frame Assembly in Bypass Mode
          5. 7.3.6.1.5 JESD204B/C Frame Assembly With Real Decimation
          6. 7.3.6.1.6 JESD204B,C Frame Assembly With Complex Decimation
        2. 7.3.6.2 JESD Output Reference Clock
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device Operating Mode Comparison
    5. 7.5 Programming
      1. 7.5.1 GPIO Control
      2. 7.5.2 SPI Register Write
      3. 7.5.3 SPI Register Read
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application: Spectrum Analyzer
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Input Signal Path: Wideband Receiver
        2. 8.2.1.2 Clocking
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Sampling Clock Requirements
      3. 8.2.3 Application Performance Plots
    3. 8.3 Typical Application: Time Domain Digitizer
      1. 8.3.1 Design Requirements
        1. 8.3.1.1 Input Signal Path: Time Domain Digitizer
      2. 8.3.2 Application Performance Plots
    4. 8.4 Initialization Set Up
    5. 8.5 Power Supply Recommendations
    6. 8.6 Layout
      1. 8.6.1 Layout Guidelines
      2. 8.6.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
      2. 9.1.2 Third-Party Products Disclaimer
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
7.3.5.5.4.2 NCO RESET

The NCO phase accumulator can be reset for each NCO through an nco_reset signal. The NCO reset can be masked for each DDC (nco_reset_mask[7:0]). The NCO reset signal can be sourced from software (sw_nco_sync) or the NCOs can be armed through a GPIO to be reset on the next SYSREF edge.

ADC32RF72 NCO RESET With All Control SignalsFigure 7-33 NCO RESET With All Control Signals

The gpio_nco_arm NCO reset path is used to synchronize multiple NCOs across devices from a host device. The host device can launch the gpio_nco_arm on the falling edge of the SYSREF to give the maximum time for the gpio_nco_arm signal to reach all devices prior to the next SYSREF edge.

The following registers can be programmed:

Table 7-15 Mixer and NCO Programming

System Parameter

Name		SizeDefaultAccessDescription
DDC_NCO_UPDATE_SRC_SEL10R/W

Select the source of the NCO update signal.

0: The NCO update signal is sourced from software.

1: Leaking the internal SYSREF (SYSREF_DIG) to update the NCOs.

DDC_NCO_RESET_SRC_SEL10R/W

Select the source of the NCO reset signal.

0: The NCO reset signal is sourced from software.

1: The GPIO arm signal (gpio_nco_arm) arms the NCO module so that an NCO update signal is issued on the next rising edge of SYSREF.

DDC_NCO_UPDATE_MASK80R/W

Per DDC NCO update signal masking control. If the NCO update source is from software, DDC[x] and DDC[x+1], where x ∈ {0,2,4,6}, must be configured identically. Setting the mask bit to 1 makes sure the respective DDC NCOs are masked from the NCO update signal.

Bit 0: DDC0 NCO update mask control.

Bit 1: DDC1 NCO update mask control.

Bit 2: DDC2 NCO update mask control.

Bit 3: DDC3 NCO update mask control.

Bit 4: DDC4 NCO update mask control.

Bit 5: DDC5 NCO update mask control.

Bit 6: DDC6 NCO update mask control.

Bit 7: DDC7 NCO update mask control.

DDC_NCO_RESET_MASK80R/W

Per DDC NCO reset signal masking control. If the NCO reset source is from software, DDC[x] and DDC[x+1], where x ∈ {0,2,4,6}, must be configured identically. Setting the mask bit to 1 makes sure the respective DDC NCOs are masked from the NCO reset signal.

Bit 0: DDC0 NCO update reset control.

Bit 1: DDC1 NCO update reset control.

Bit 2: DDC2 NCO update reset control.

Bit 3: DDC3 NCO update reset control.

Bit 4: DDC4 NCO update reset control.

Bit 5: DDC5 NCO update reset control.

Bit 6: DDC6 NCO update reset control.

Bit 7: DDC7 NCO update reset control.

DDC{0..7}_NCO_HOP_SRC_SEL10R/W

Select the source of the NCO hoping signal for the DDC.

0: NCO selection (frequency hopping) through GPIO (one GPIO function per DDC).

1: NCO selection (frequency hopping) through software.

DDC{0..7}_NCO_HOP_MODE10R/W

Select the NCO mode when hopping.

0: Not used

1: Phase coherent hopping mode where the original phase of the NCOs is always maintained across hops.

DDC{0..7}_NCO{0,1}_FCW480R/W48-bit FCW word for NCO{0,1}
DDC{0..7}_NCO{0,1}_PHASE190R/W19-bit phase offset for NCO{0,1}