SBASAL2 November   2025 ADC32RF72

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics - Power Consumption
    6. 5.6 Electrical Characteristics - DC Specifications
    7. 5.7 Electrical Characteristics - AC Specifications
    8. 5.8 Timing Requirements
    9. 5.9 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Inputs
        1. 7.3.1.1 Input Bandwidth
        2. 7.3.1.2 Background Calibration
      2. 7.3.2 ADC Channel Selection and Power Down Modes
      3. 7.3.3 Sampling Clock Input
      4. 7.3.4 SYSREF
        1. 7.3.4.1 SYSREF Monitor
      5. 7.3.5 Digital Signal Processor (DSP) Features
        1. 7.3.5.1 DSP Input Mux
        2. 7.3.5.2 Fractional Delay
        3. 7.3.5.3 Programmable FIR Filter for Equalization
        4. 7.3.5.4 DSP Output Mux
        5. 7.3.5.5 Digital Down Converter (DDC)
          1. 7.3.5.5.1 Decimation Filter Input
          2. 7.3.5.5.2 Decimation Modes
          3. 7.3.5.5.3 Decimation Filter Response
          4. 7.3.5.5.4 Numerically Controlled Oscillator (NCO)
            1. 7.3.5.5.4.1 NCO Update
            2. 7.3.5.5.4.2 NCO RESET
      6. 7.3.6 Digital Output Interface
        1. 7.3.6.1 JESD204B/C Interface
          1. 7.3.6.1.1 JESD204B Initial Lane Alignment (ILA)
          2. 7.3.6.1.2 SYNC Signal
          3. 7.3.6.1.3 JESD204B/C Frame Assembly
          4. 7.3.6.1.4 JESD204B/C Frame Assembly in Bypass Mode
          5. 7.3.6.1.5 JESD204B/C Frame Assembly With Real Decimation
          6. 7.3.6.1.6 JESD204B,C Frame Assembly With Complex Decimation
        2. 7.3.6.2 JESD Output Reference Clock
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device Operating Mode Comparison
    5. 7.5 Programming
      1. 7.5.1 GPIO Control
      2. 7.5.2 SPI Register Write
      3. 7.5.3 SPI Register Read
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application: Spectrum Analyzer
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Input Signal Path: Wideband Receiver
        2. 8.2.1.2 Clocking
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Sampling Clock Requirements
      3. 8.2.3 Application Performance Plots
    3. 8.3 Typical Application: Time Domain Digitizer
      1. 8.3.1 Design Requirements
        1. 8.3.1.1 Input Signal Path: Time Domain Digitizer
      2. 8.3.2 Application Performance Plots
    4. 8.4 Initialization Set Up
    5. 8.5 Power Supply Recommendations
    6. 8.6 Layout
      1. 8.6.1 Layout Guidelines
      2. 8.6.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
      2. 9.1.2 Third-Party Products Disclaimer
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
7.3.6.1.6 JESD204B,C Frame Assembly With Complex Decimation

Table 7-24 lists the available JESD204B,C interface configurations and corresponding SerDes lane rates. The boundary conditions are:

  • JESD204B: lane rates from 4 (min) to 15Gpbs (max)
  • JESD204C: lane rates from 4 (min) to 24.75Gbps (max)

The JESD204B/C frame assemblies are shown in Table 7-25 (16-bit) and Table 7-29 (24-bit).

When using octal band DDC, two separate JESD links need to be configured because the M (# of converters per link) cannot exceed 8 as shown in Table 7-25. For example for octal band DDC using 8 JESD lanes each of the two links can be configured as LMFS = 4-8-4-1. The internal JESD output mux can be used to assign specific SerDes lanes to each link.

Table 7-24 JESD Mode Options: Complex Decimation
Output
Resolution
(bit)		LMFSJESD204B:
Lane Rate (Gbps)		JESD204B:
RATIO
[fSERDES/(FS/N)]		JESD204C:
Lane Rate (Gbps)		JESD204C:
RATIO
[fSERDES/(FS/N)]
168821FS × 16 × 10 / 8 × M / D / L20FS × 16 × 66 / 64 × M / D / L16.5
48414033
28818066
18161160132
8411108.25
44212016.5
24414033
14818066
821254.125
4211108.25
22212016.5
12414033
248831FS × 24 × 10 / 8 × M / D / L30FS × 24 × 66 / 64 × M / D / L24.75
48616049.5
2812112099
18241240198
84321512.375
44313024.75
24616049.5
1412112099
82347.56.1875
42321512.375
22323024.75
12616049.5

D: complex decimation setting

Table 7-25 Example JESD Frame Assembly: Complex Decimation, Octal Band, 16-bit Output
Note: the LMFS configuration is Per JESD Link
JESD
LINK		OUTPUT
LANE		LMFS =
4-8-4-1		LMFS =
2-8-8-1		LMFS =
1-8-16-1
LINK0STX0AI0 [15:0], AQ0 [15:0]AI0 [15:0], AQ0 [15:0]BI0 [15:0], BQ0 [15:0]AI0 [15:0], AQ0 [15:0]BI0 [15:0], BQ0 [15:0]CI0 [15:0], CQ0 [15:0]DI0 [15:0], DQ0 [15:0]
STX1BI0 [15:0], BQ0 [15:0]CI0 [15:0], CQ0 [15:0]DI0 [15:0], DQ0 [15:0]
STX2CI0 [15:0], CQ0 [15:0]
STX3DI0 [15:0], DQ0 [15:0]
LINK1STX4EI0 [15:0], EQ0 [15:0]EI0 [15:0], EQ0 [15:0]FI0 [15:0], FQ0 [15:0]EI0 [15:0], EQ0 [15:0]FI0 [15:0], FQ0 [15:0]GI0 [15:0], GQ0 [15:0]HI0 [15:0], HQ0 [15:0]
STX5FI0 [15:0], FQ0 [15:0]GI0 [15:0], GQ0 [15:0]HI0 [15:0], HQ0 [15:0]
STX6GI0 [15:0], GQ0 [15:0]
STX7HI0 [15:0], HQ0 [15:0]
Table 7-26 Example JESD Frame Assembly: Complex Decimation, Quad Band, 16-bit Output
OUTPUT
LANE		LMFS =
8-8-2-1		LMFS =
4-8-4-1		LMFS =
2-8-8-1		LMFS =
1-8-16-1
STX0AI0 [15:0]AI0 [15:0], AQ0 [15:0]AI0 [15:0], AQ0 [15:0]BI0 [15:0], BQ0 [15:0]AI0 [15:0], AQ0 [15:0]BI0 [15:0], BQ0 [15:0]CI0 [15:0], CQ0 [15:0]DI0 [15:0], DQ0 [15:0]
STX1 AQ0 [15:0]BI0 [15:0], BQ0 [15:0]CI0 [15:0], CQ0 [15:0]DI0 [15:0], DQ0 [15:0]
STX2BI0 [15:0]CI0 [15:0], CQ0 [15:0]
STX3 BQ0 [15:0]DI0 [15:0], DQ0 [15:0]
STX4CI0 [15:0]
STX5 CQ0 [15:0]
STX6DI0 [15:0]
STX7DQ0 [15:0]
Table 7-27 Example JESD Frame Assembly: Complex Decimation, Dual Band, 16-bit Output
OUTPUT
LANE		LMFS =
8-4-1-1		LMFS =
4-4-2-1		LMFS =
2-4-4-1		LMFS =
1-4-8-1
STX0AI0 [15:8]AI0 [15:0]AI0 [15:0]AQ0 [15:0]AI0 [15:0]AQ0 [15:0]BI0 [15:0]BQ0 [15:0]
STX1AI0 [7:0]AQ0 [15:0]BI0 [15:0]BQ0 [15:0]
STX2AQ0 [15:8]BI0 [15:0]
STX3AQ0 [7:0]BQ0 [15:0]
STX4BI0 [15:8]
STX5BI0 [7:0]
STX6BQ0 [15:8]
STX7BQ0 [7:0]
Table 7-28 Example JESD Frame Assembly: Complex Decimation, Single Band, 16-bit Output
OUTPUT
LANE		LMFS =
8-2-1-2		LMFS =
4-2-1-1		LMFS =
2-2-2-1		LMFS =
1-2-4-1
STX0AI0 [15:8]AI0 [15:8]AI0 [15:8]AI0 [7:0]AI0 [15:8]AI0 [7:0]AQ0 [15:8]AQ0 [7:0]
STX1AI0 [7:0]AI0 [7:0]AQ0 [15:8]AQ0 [7:0]
STX2AQ0 [15:8]AQ0 [15:8]
STX3AQ0 [7:0]AQ0 [7:0]
STX4AI1 [15:8]
STX5AI1 [7:0]
STX6AQ1 [15:8]
STX7AQ1 [7:0]
Table 7-29 Example JESD Frame Assembly: Complex Decimation, Octal Band, 24-bit Output
Note: the LMFS configuration is Per JESD Link
JESD
LINK		OUTPUT
LANE		LMFS =
4-8-6-1		LMFS =
2-8-12-1		LMFS =
1-8-24-1
LINK0STX0AI0 [23:0], AQ0 [23:0] AI0 [23:0], AQ0 [23:0] BI0 [23:0], BQ0 [23:0]AI0 [23:0], AQ0 [23:0] BI0 [23:0], BQ0 [23:0]CI0 [23:0], CQ0 [23:0]DI0 [23:0], DQ0 [23:0]
STX1BI0 [23:0], BQ0 [23:0]CI0 [23:0], CQ0 [23:0]DI0 [23:0], DQ0 [23:0]
STX2CI0 [23:0], CQ0 [23:0]
STX3DI0 [23:0], DQ0 [23:0]
LINK1STX4EI0 [23:0], EQ0 [23:0] EI0 [23:0], EQ0 [23:0] FI0 [23:0], FQ0 [23:0]EI0 [23:0], EQ0 [23:0] FI0 [23:0], FQ0 [23:0]GI0 [23:0], GQ0 [23:0]HI0 [23:0], HQ0 [23:0]
STX5FI0 [23:0], FQ0 [23:0]GI0 [23:0], GQ0 [23:0]HI0 [23:0], HQ0 [23:0]
STX6GI0 [23:0], GQ0 [23:0]
STX7HI0 [23:0], HQ0 [23:0]
Table 7-30 Example JESD Frame Assembly: Complex Decimation, Quad Band, 24-bit Output
OUTPUT
LANE		LMFS =
8-8-3-1		LMFS =
4-8-6-1		LMFS =
2-8-12-1		LMFS =
1-8-24-1
STX0AI0 [23:0] AI0 [23:0], AQ0 [23:0] AI0 [23:0], AQ0 [23:0] BI0 [23:0], BQ0 [23:0]AI0 [23:0], AQ0 [23:0] BI0 [23:0], BQ0 [23:0]CI0 [23:0], CQ0 [23:0]DI0 [23:0], DQ0 [23:0]
STX1AQ0 [23:0] BI0 [23:0], BQ0 [23:0]CI0 [23:0], CQ0 [23:0]DI0 [23:0], DQ0 [23:0]
STX2BI0 [23:0]CI0 [23:0], CQ0 [23:0]
STX3BQ0 [23:0]DI0 [23:0], DQ0 [23:0]
STX4CI0 [23:0]
STX5CQ0 [23:0]
STX6DI0 [23:0]
STX7DQ0 [23:0]
Table 7-31 Example JESD Frame Assembly: Complex Decimation, Dual Band, 24-bit Output
OUTPUT
LANE		LMFS =
8-4-3-2		LMFS =
4-4-3-1		LMFS =
2-4-6-1		LMFS =
1-4-12-1
STX0AI0 [23:0]AI0 [23:0]AI0 [23:0]AQ0 [23:0]AI0 [23:0]AQ0 [23:0]BI0 [23:0]BQ0 [23:0]
STX1AQ0 [23:0]AQ0 [23:0]BI0 [23:0]BQ0 [23:0]
STX2AI1 [23:0]BI0 [23:0]
STX3AQ1 [23:0]BQ0 [23:0]
STX4BI0 [23:0]
STX5BQ0 [23:0]
STX6BI1 [23:0]
STX7BQ1 [23:0]
Table 7-32 Example JESD Frame Assembly: Complex Decimation, Single Band, 24-bit Output
OUTPUT
LANE		LMFS =
8-2-3-4		LMFS =
4-2-3-2		LMFS =
2-2-3-1		LMFS =
1-2-6-1
STX0AI0 [23:0]AI0 [23:0]AI0 [23:0]AI0 [23:0]AQ0 [23:0]
STX1AQ0 [23:0]AQ0 [23:0]AQ0 [23:0]
STX2AI1 [23:0]AI1 [23:0]
STX3AQ1 [23:0]AQ1 [23:0]
STX4AI2 [23:0]
STX5AQ2 [23:0]
STX6AI3 [23:0]
STX7AQ3 [23:0]