SLAA559E April   2014  – November 2016 MSP430AFE221 , MSP430AFE222 , MSP430AFE223 , MSP430AFE231 , MSP430AFE232 , MSP430AFE233 , MSP430AFE251 , MSP430AFE252 , MSP430AFE253 , MSP430F2001 , MSP430F2002 , MSP430F2003 , MSP430F2011 , MSP430F2012 , MSP430F2013 , MSP430F2013-EP , MSP430F2101 , MSP430F2111 , MSP430F2112 , MSP430F2121 , MSP430F2122 , MSP430F2131 , MSP430F2132 , MSP430F2232 , MSP430F2234 , MSP430F2252 , MSP430F2254 , MSP430F2272 , MSP430F2274 , MSP430F233 , MSP430F2330 , MSP430F235 , MSP430F2350 , MSP430F2370 , MSP430F2410 , MSP430F2416 , MSP430F2417 , MSP430F2418 , MSP430F2419 , MSP430F247 , MSP430F2471 , MSP430F248 , MSP430F2481 , MSP430F249 , MSP430F2491 , MSP430F2616 , MSP430F2617 , MSP430F2618 , MSP430F2619 , MSP430FR5847 , MSP430FR58471 , MSP430FR5848 , MSP430FR5849 , MSP430FR5857 , MSP430FR5858 , MSP430FR5859 , MSP430FR5867 , MSP430FR58671 , MSP430FR5868 , MSP430FR5869 , MSP430FR5870 , MSP430FR5872 , MSP430FR58721 , MSP430FR5887 , MSP430FR5888 , MSP430FR5889 , MSP430FR58891 , MSP430FR5922 , MSP430FR59221 , MSP430FR5947 , MSP430FR59471 , MSP430FR5948 , MSP430FR5949 , MSP430FR5957 , MSP430FR5958 , MSP430FR5959 , MSP430FR5967 , MSP430FR5968 , MSP430FR5969 , MSP430FR59691 , MSP430FR5970 , MSP430FR5972 , MSP430FR59721 , MSP430FR5986 , MSP430FR5987 , MSP430FR5988 , MSP430FR5989 , MSP430FR5989-EP , MSP430FR59891 , MSP430FR5994 , MSP430FR6820 , MSP430FR6822 , MSP430FR68221 , MSP430FR6870 , MSP430FR6872 , MSP430FR68721 , MSP430FR6877 , MSP430FR6879 , MSP430FR68791 , MSP430FR6887 , MSP430FR6888 , MSP430FR6889 , MSP430FR68891 , MSP430FR6920 , MSP430FR6922 , MSP430FR69221 , MSP430FR6927 , MSP430FR69271 , MSP430FR6928 , MSP430FR6970 , MSP430FR6972 , MSP430FR69721 , MSP430FR6977 , MSP430FR6979 , MSP430FR69791 , MSP430FR6987 , MSP430FR6988 , MSP430FR6989 , MSP430FR69891 , MSP430G2001 , MSP430G2101 , MSP430G2102 , MSP430G2111 , MSP430G2112 , MSP430G2121 , MSP430G2131 , MSP430G2132 , MSP430G2152 , MSP430G2153 , MSP430G2201 , MSP430G2202 , MSP430G2203 , MSP430G2210 , MSP430G2211 , MSP430G2212 , MSP430G2213 , MSP430G2221 , MSP430G2230 , MSP430G2231 , MSP430G2232 , MSP430G2233 , MSP430G2252 , MSP430G2253 , MSP430G2302 , MSP430G2303 , MSP430G2312 , MSP430G2313 , MSP430G2332 , MSP430G2333 , MSP430G2352 , MSP430G2353 , MSP430G2402 , MSP430G2403 , MSP430G2412 , MSP430G2413 , MSP430G2432 , MSP430G2433 , MSP430G2452 , MSP430G2453 , MSP430G2513 , MSP430G2533 , MSP430G2553

 

  1.   Migrating from the MSP430F2xx and MSP430G2xx Families to the MSP430FR58xx/FR59xx/68xx/69xx Family
    1.     Trademarks
    2. 1 Introduction
    3. 2 In-System Programming of Nonvolatile Memory
      1. 2.1 Ferroelectric RAM (FRAM) Overview
      2. 2.2 FRAM Cell
      3. 2.3 Protecting FRAM Using the Memory Protection Unit
        1. 2.3.1 Dynamically Partitioning FRAM
      4. 2.4 FRAM Memory Wait States
      5. 2.5 Bootloader (BSL)
      6. 2.6 JTAG and Security
      7. 2.7 Production Programming
    4. 3 Hardware Migration Considerations
    5. 4 Device Calibration Information
    6. 5 Important Device Specifications
    7. 6 Core Architecture Considerations
      1. 6.1 Power Management Module (PMM)
      2. 6.2 Clock System
      3. 6.3 Operating Modes, Wakeup, and Reset
      4. 6.4 Determining the Cause of Reset
      5. 6.5 Interrupt Vectors
      6. 6.6 FRAM and the FRAM Controller
        1. 6.6.1 Flash and FRAM Overview Comparison
        2. 6.6.2 Cache Architecture
      7. 6.7 RAM Controller (RAMCTL)
    8. 7 Peripheral Considerations
      1. 7.1 Watchdog Timer
      2. 7.2 Ports
        1. 7.2.1 Digital Input/Output
        2. 7.2.2 Capacitive Touch I/O
      3. 7.3 Analog-to-Digital Converters
        1. 7.3.1 ADC12 to ADC12_B
        2. 7.3.2 ADC10 to ADC12_B
      4. 7.4 REF_A Module
      5. 7.5 Comparator_A to Comparator_E
      6. 7.6 Hardware Multiplier (HWMPY32)
      7. 7.7 DMA Controller
      8. 7.8 Low-Energy Accelerator (LEA) for Signal Processing
      9. 7.9 Communication Modules
        1. 7.9.1 USI to eUSCI
        2. 7.9.2 USCI to eUSCI
    9. 8 Conclusion
    10. 9 References
  2.   Revision History

6.3 Operating Modes, Wakeup, and Reset

Table 3 compares the operating modes that are available and the wake-up times from LPMs.

Table 3. Comparison of Operating Modes and Wake-up Times

Parameter or Feature FR59xx F2xx
LPM0, LPM1, LPM2, LPM3, LPM4 Available Available
LPM3.5, LPM4.5 Available Not available
Wake-up time from LPM0 1.5 × fDCO
≈ 1.5 µs (fDCO = 1 MHz)		 2 µs
Wake-up time from LPM1 or LPM2(1) 6 µs 2 µs
Wake-up time from LPM3 or LPM4(1) 7 µs 2 µs
Wake-up time from LPM3.5 (1) 250 µs Not applicable
Wake-up time from BOR event(1) 1.5 ms (max) 2 ms (max)
(1) The values in this table are approximations; to find the values for a specific device, see the data sheet.

The code flow for entry into and exit out of low-power modes LPM0 to LPM4 remains the same in the FR59xx family as in the F2xx family. There are differences in functionality between the low-power modes on the F2xx compared to the FR59xx devices. These differences are described in the SYS chapter of the MSP430FR58xx, MSP430FR59xx, MSP430FR68xx, and MSP430FR69xx Family User's Guide.

Two new low-power modes introduced in the FR59xx family are LPM3.5 and LPM4.5. In both modes, the VCORE LDO is turned off, powering down the digital core, RAM, and peripherals. To wake up from LPM3.5, self-timed RTC interrupts or port interrupts are required. All other system interrupts are not available. The RTC module on the FR59xx device is powered from the VCC rail and can, therefore, stay functional even when the core voltage is turned off. In LPM4.5, only port interrupts can be used to wake up the device.

It is important to understand that the LPMx.5 modes are inherently different from the typical LPMs (LPM0 through LPM4) in that a wake-up from these modes constitutes a device reset. Because RAM is not retained, the state of the application (if stored in variables located in RAM) and register initialization is lost. These modes are suited for applications that spend large amounts of time in 'deep sleep' and where wake-up time is not critical. Also, the frequency of wake up needs to be considered because there is an energy penalty associated with the time spent during wake-up. For example, a 2xx application that wakes up every 1 ms from LPM3 to sample a signal can be more efficiently ported to LPM3 in FR59xx rather than LPM3.5. This is because LPM3.5 requires approximately 250 µs to wake up, and the application will spend 25% of its duty cycle during wake-up, which significantly impacts the power gains that were achieved in moving from LPM3 to LPM3.5.

Consider a different application that wakes up once per minute to update a time stamp. In this case, LPM3.5 could be a better fit for maximizing power savings, because the average power during on time for LPM3.5 is 50% that of LPM3. Hence, selecting LPMs when migrating depends on the application and the on/off duty cycle that is required.

One important difference between the families is the behavior on reset. There are multiple levels of reset across all MSP430 families such as PUC, POR, and BOR. In the F2xx family, the program counter (PC) is reinitialized to the reset vector location on executing a PUC. In the case of a power cycle (POR), the PC is reinitialized after tDBOR has elapsed [4]. In the FR59xx family, the behavior on executing a PUC is the same as the F2xx family as regards re-initialization of the PC and specific peripheral registers.

However, a deeper level of reset such as POR or BOR executes a boot code that is present in protected ROM. This boot code sets up the device and loads calibration settings that are essential to establish device functionality. Hence, the time to start up from a POR or BOR in the FR59xx family is different from the time in the F2xx family. For details, see the device-specific data sheet.

The FR59xx can also initiate all levels of reset in software (in the F2xx family, only a PUC can be initiated by software). The resets are initiated by setting the PMMSWBOR and PMMSWPOR bits in the PMMCTL0 control register.