SLASFL3 Data sheet

SLASFL3 September 2026 DAC90802

PRODUCTION DATA

7.1 COMMON Registers

Table 7-1 lists the memory-mapped registers for the COMMON registers. All register offset addresses not listed in Table 7-1 should be considered as reserved locations and the register contents should not be modified.

Table 7-1 COMMON Registers

Address	Acronym	Bit 31	Bit 30	Bit 29	Bit 28	Bit 27	Bit 26	Bit 25	Bit 24
		Bit 23	Bit 22	Bit 21	Bit 20	Bit 19	Bit 18	Bit 17	Bit 16
		Bit 15	Bit 14	Bit 13	Bit 12	Bit 11	Bit 10	Bit 9	Bit 8
		Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
0x00	NOP	NOP
		NOP
		NOP
		NOP
0x01	DEVICE_CFG	DAC_CONFIG_CH1					DAC_CONFIG_CH0
		DAC_CONFIG_CH0		VOSADJ_EN1	TEMP_SEL1		RESERVED	VOSADJ_EN0	TEMP_SEL0
		TEMP_SEL0	RESERVED		POL_CFG1	POL_CFG0	EN_CH1	EN_CH0	DEVICE_ID
		DEVICE_ID				VERSION_ID
0x02	DEVICE_CTRL	RESERVED
		RESERVED
		RESERVED					SFT_LDAC	BOOT	BOOT_FAIL
		SFT_RST
0x03	CH0_CFG	RESERVED
		RESERVED							OFS_EN0
		RESERVED		RESERVED	ASYNC_UPDT_0	SFT_LDAC_EN0	GAIN_CH0		VREF_SQ0
		VREF_SQ0
0x04	CH1_CFG	RESERVED
		RESERVED							OFS_EN1
		RESERVED		RESERVED	ASYNC_UPDT_1	SFT_LDAC_EN1	GAIN_CH1		VREF_SQ1
		VREF_SQ1
0x05	SPI_CFG	RESERVED
		RESERVED
		RESERVED
		RESERVED	SPI_DCH	SPI_STR	FSDO_EN	SDO_EN	SPI_DDR	SPI_MIO
0x08	ALERT_CFG	TSD_LVL1						TSD_LVL0
		TSD_LVL0				RESERVED
		RESERVED				TMPALRT_1	TMPALRT_0	TMPALRT_L1	TMPALRT_L0
		TMPALRT_CLR	TMPALRT_ACT			TMPALRT_MSK		TMPALRT_LAP	TMPALRT_ENP

Complex bit access types are encoded to fit into small table cells. Table 7-2 shows the codes that are used for access types in this section.

Table 7-2 COMMON Access Type Codes

Access Type	Code	Description
Read Type
R	R	Read
Write Type
W	W	Write
WtoPH	W	Write
Reset or Default Value
-n		Value after reset or the default value

7.1.1 NOP Register (Address = 0x00) [Reset = 0x00000000]

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Table 7-3 NOP Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	NOP	R/W	0x0	No-Operation. Read Only Register . 0x0 = Default Value

7.1.2 DEVICE_CFG Register (Address = 0x01) [Reset = 0x000000B3]

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Table 7-4 DEVICE_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-27	DAC_CONFIG_CH1	R/W	0x0	DAC application mode selection for channel 1. Unlisted field values are RESERVED. 00h = AWG Mode 01h = Fast Settling Mode 02h = Multiplying Mode
26-22	DAC_CONFIG_CH0	R/W	0x0	DAC application mode selection for channel 0. Unlisted field values are RESERVED. 00h = AWG Mode 01h = Fast Settling Mode 02h = Multiplying Mode
21	VOSADJ_EN1	R/W	0x0	Enable the VOSADJ1 input for channel 1. 0x0 = VOSADJ input disabled. 0x1 = VOSADJ input enabled.
20-19	TEMP_SEL1	R/W	0x0	Temperature output TEMP1 output signal selection for channel 1. 0x0 = Temperature output disabled. 0x1 = Temperature output enabled in analog output mode. 0x2 = Temperature output enabled in TSD mode.
18	RESERVED	R	0x0
17	VOSADJ_EN0	R/W	0x0	Enable the VOSADJ0 input for channel 0. 0x0 = VOSADJ input disabled. 0x1 = VOSADJ input enabled.
16-15	TEMP_SEL0	R/W	0x0	Temperature output TEMP0 output signal selection for channel 0. 0x0 = Temperature output disabled. 0x1 = Temperature output enabled in analog output mode. 0x2 = Temperature output enabled in TSD mode.
14-13	RESERVED	R	0x0
12	POL_CFG1	R/W	0x0	Unipolar / Bipolar DAC configuration for channel 1. 0x0 = DAC unipolar configuration. 0x1 = DAC bipolar configuration.
11	POL_CFG0	R/W	0x0	Unipolar / Bipolar DAC configuration for channel 0. 0x0 = DAC unipolar configuration. 0x1 = DAC bipolar configuration.
10	EN_CH1	R/WtoPH	0x0	Channel enable (power up) control for channel 1. 0x0 = Channel disable (power down) 0x1 = Channel enable (power up). This bit self-resets in case of an alert.
9	EN_CH0	R/WtoPH	0x0	Channel enable (power up) control for channel 0. 0x0 = Channel disable (power down) 0x1 = Channel enable (power up). This bit self-resets in case of an alert.
8-4	DEVICE_ID	R	0xB	Device Identifier (Read Only)
3-0	VERSION_ID	R	0x3	Version Identifier (Read Only)

7.1.3 DEVICE_CTRL Register (Address = 0x02) [Reset = 0x00000000]

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Table 7-5 DEVICE_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESERVED	R	0x0
30-11	RESERVED	R	0x0
10	SFT_LDAC	R/WtoPH	0x0	Software controlled LDAC signal. Simultaneously asserts LDAC for both channels. Channel and SFT_LDAC_EN for the channel must both be enabled to receive the LDAC assertion. 0x0 = Assert LDAC. This bit is self-resetting.
9	BOOT	R	0x0	Bit to indicate device bootup in progress after POR. (Read Only) 0x0 = Device not in boot sequence 0x1 = Device executing boot sequence
8	BOOT_FAIL	R	0x0	Read only signal indicating the device bootup has failed and there's issue with the OTP. 0x0 = Device passed boot up sequence 0x1 = Device passed boot up sequence
7-0	SFT_RST	R/W	0x0	Code for software controlled reset signal . Equivalent to asserting the hardware RESET. 0xAA = Reset asserted

7.1.4 CH0_CFG Register (Address = 0x03) [Reset = 0x00000219]

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Table 7-6 CH0_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-30	RESERVED	R	0x0
29	RESERVED	R	0x0
28-26	RESERVED	R	0x0
25-22	RESERVED	R	0x0
21-17	RESERVED	R	0x0
16	OFS_EN0	R/W	0x0	Enable ROFS for channel-0. This is used to give an asymmetric push to the output depending on the voltage applied on the ROFS pin
15-14	RESERVED	R	0x0
13	RESERVED	R	0x0
12	ASYNC_UPDT_0	R/W	0x0	Sets the DAC0 register update mode 0x0 = asynchronous update mode 0x1 = synchronous update mode
11	SFT_LDAC_EN0	R/W	0x0	Enabling soft ldac for channel0
10-9	GAIN_CH0	R/W	0x1	Channel 0 Voltage Gain Selection 0x0 = Gain 1 × 0x1 = Gain 4 × 0x2 = Gain 2 ×
8-0	VREF_SQ0	R/W	0x19	(Gain * Voltage Reference)² has to be set in this Reg

7.1.5 CH1_CFG Register (Address = 0x04) [Reset = 0x00000219]

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Table 7-7 CH1_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-30	RESERVED	R	0x0
29	RESERVED	R	0x0
28-26	RESERVED	R	0x0
25-22	RESERVED	R	0x0
21-17	RESERVED	R	0x0
16	OFS_EN1	R/W	0x0	Enable ROFS for channel-1. This is used to give an asymmetric push to the output depending on the voltage applied on the ROFS pin
15-14	RESERVED	R	0x0
13	RESERVED	R	0x0
12	ASYNC_UPDT_1	R/W	0x0	Sets the DAC0 register update mode 0x0 = asynchronous update mode 0x1 = synchronous update mode
11	SFT_LDAC_EN1	R/W	0x0	Enabling soft ldac for channel0
10-9	GAIN_CH1	R/W	0x1	Channel 1 Voltage Gain Selection 0x0 = Gain 1 × 0x1 = Gain 4 × 0x2 = Gain 2 ×
8-0	VREF_SQ1	R/W	0x19	(Gain × Voltage Reference)² has to be set in this register

7.1.6 SPI_CFG Register (Address = 0x05) [Reset = 0x00000000]

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Table 7-8 SPI_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESERVED	R	0x0
30-7	RESERVED	R	0x0
6	SPI_DCH	R/W	0x0	SPI Daisy Chain mode enable / disable bit. 0x0 = Daisy Chain Mode Disabled 0x1 = Daisy Chain Mode Enabled
5	SPI_STR	R/W	0x0	Stream Mode configurations 0x0 = Dual Channel Stream Enabled 0x1 = Single Channel Stream Enabled
4	FSDO_EN	R/W	0x0	SDO latching control 0x0 = No Latch at the SDO port 0x1 = Output will be Latched
3	SDO_EN	R/W	0x0	SDO Enable Control 0x0 = SDO ports get disabled 0x1 = SDO ports enabled
2	SPI_DDR	R/W	0x0	DDR Mode Enable 0x0 = SDR Mode (Single Data Rate) 0x1 = DDR Mode (Double Data Rate)
1-0	SPI_MIO	R/W	0x0	SPI IO Modes Control 0x0 = Standard SPI 0x1 = Dual SPI 0x2 = Quad SPI 0x3 = Reserved

7.1.7 ALERT_CFG Register (Address = 0x08) [Reset = 0xEFB0001E]

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Table 7-9 ALERT_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-26	TSD_LVL1	R/W	0x3B	Code for Temp Shut Down Threshold (Reset Value : 6x3B : 140°C) 0x0 = 30°C 0x3F = 150°C
25-20	TSD_LVL0	R/W	0x3B	Code for Temp Shut Down Threshold (Reset Value : 6x3B : 140°C) 0x0 = 30°C 0x3F = 150°C
19-18	RESERVED	R	0x0
17-16	RESERVED	R	0x0
15-12	RESERVED	R	0x0
11	TMPALRT_1	R	0x0	Read Only Signal indicating the Non-Latched Temp Alert
10	TMPALRT_0	R	0x0	Read Only Signal indicating the Non-Latched Temp Alert
9	TMPALRT_L1	R	0x0	Read Only Signal indicating the Latched Temp Alert
8	TMPALRT_L0	R	0x0	Read Only Signal indicating the Latched Temp Alert
7	TMPALRT_CLR	R/WtoPH	0x0	Latched temperature alerts clear command 0x0 = No action 0x1 = Latched temperature alert clear. This bit is self-resetting.
6-4	TMPALRT_ACT	R/W	0x1	Response to temperature alert being asserted. Unlisted field values are RESERVED 0x0 = No action. 0x1 = Shut-down asserting channel only when alert is asserted. No power up allowed until latched synchronous alert goes low 0x2 = Shut-down asserting channel only with alert is asserted. Power up is allowed anytime after assertion. 0x5 = Shut down all channels when alert is asserted onnay channel. No power up allowed until latched synchronous alert goes low. 0x6 = Shut down all channelswhen alert is asserted onnay channel. Power up is allowed anytime after assertion.
3-2	TMPALRT_MSK	R/W	0x3	Temperature alert masking on TEMP Pin. 0x0 = Alerts are masked (On TEMP Pin) 0x3 = (dafault) alerts are un masked (On TEMP Pin) Unlisted bits are reserved
1	TMPALRT_LAP	R/W	0x1	Latched temperature alerts on TEMP pin 0x0 = Disable 0x1 = Enable
0	TMPALRT_ENP	R/W	0x0	Temperature alerts on TEMP pin (non-latched) 0x0 = Disable 0x1 = Enable