SLASFL3 September   2026 DAC90802

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Timing Diagrams
    8. 5.8 Typical Characteristics
      1. 5.8.1 Typical Characteristics: Linearity
      2. 5.8.2 Typical Characteristics: Glitch
      3. 5.8.3 Typical Characteristics: Multiplying Mode
      4. 5.8.4 Typical Characteristics: Fast-Settling Mode
      5. 5.8.5 Typical Characteristics: AWG Mode
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Digital-to-Analog Converters
        1. 6.3.1.1 Reference
        2. 6.3.1.2 Output Span
          1. 6.3.1.2.1 Gain Overrange
        3. 6.3.1.3 Output Synchronization
        4. 6.3.1.4 Thermal Sensors
      2. 6.3.2 Power-On
      3. 6.3.3 Serial Data Interface
        1. 6.3.3.1 SPI Configurations
        2. 6.3.3.2 SPI Stream Mode
        3. 6.3.3.3 SPI Daisy Chain Mode
    4. 6.4 Device Functional Modes
      1. 6.4.1 AWG Mode
      2. 6.4.2 Fast Settling Mode
      3. 6.4.3 Multiplying Mode
  8. 7 Register Maps
    1. 7.1 COMMON Registers
    2. 7.2 HS_DATA Registers
    3. 7.3 HR_DATA Registers
  9. 8 Application and Implementation
    1. 8.1 Application
    2. 8.2 Design Requirements
      1. 8.2.1 Reference Signal Chain Information
        1. 8.2.1.1 DC Reference
        2. 8.2.1.2 AC Reference
      2. 8.2.2 Optimising the Self-Heating Trim to Achieve Lowest THD Across Frequencies for High Voltage Swing
      3. 8.2.3 Digital Interface
      4. 8.2.4 Grounding Recommendations
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Recommendation
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Digital-to-Analog Converters

The DAC90802 implements a current-steering R-2R ladder architecture. Figure 6-1 shows a typical equivalent DAC channel. Each DAC contains a matching feedback resistor for use with the internal I-to-V conversion amplifier. The RFB pins are connected to the output of the amplifier.

DAC90802 Typical
                    Equivalent DAC Channel Figure 6-1 Typical Equivalent DAC Channel

The DAC90802 support both DC and AC reference voltage inputs. A matched internal feedback resistor network at RFB allows users to digitally select the gain GFB of the DAC output voltage either as 1V/V, 2V/V or as 4V/V. Power along with the proper gain selection must be applied to the device to achieve continuity while measuring RFB. Equation 1 defines the DAC transfer function.

Equation 1. V O U T   = -   [   G F B ∙ ( V R E F P -     V R E F P n 2 N + V R E F N n 2 N ) + G O F F ∙ V O F F + G A D J ∙   V A D J ] ∙ [ 1 + G O V ]  

Where,

G F B = R F B R D A C is the gain setting of the DAC,

n is the programmed DAC code,

N is the DAC resolution,

V R E F P ,   V R E F N are the reference voltages applied to VREFP and VREFN pins respectively,

V O F F ,   V A D J are the coarse-offset and fine-offset voltages applied to using ROFS and VOSADJ pins, respectively (see Section 6.3.1.4 for details),

G O F F = R F B R O F S ,   G A D J = R F B R V O S are the coarse-offset adjust and fine-offset adjust gains respectively (see Section 6.3.1.4 for details),

and,

V O U T is the DAC output voltage

Note: Use the DAC resolution N according to the register used to write the code n . For example, when using the 16b register in the 18-b DAC90802, N is 16.

For basic unipolar operation (without offset or adjust voltages), where V R E F P = 0 ,   V R E F N =   - V R E F

Equation 2. V O U T =   G × V R E F n 2 N

and the zero-code, mid-code and full code values are

V O U T n = 0 =   0 ,   V O U T n = 2 N - 1 = G × V R E F 2 ,   V O U T n = 2 N - 1 = G × V R E F (   1 - 1 2 N ) respectively.

For basic bipolar operation (without offset or adjust voltages), where V R E F P =   V R E F ,   V R E F N =   - V R E F

Equation 3. V O U T =   - G V R E F - 2   V R E F n 2 N = G × V R E F 2 n - 2 N 2 N

and the zero-code, mid-code and full code values are

V O U T n = 0 =   - G × V R E F ,   V O U T n = 2 N - 1 = 0 ,   V O U T n = 2 N - 1 = G × V R E F (   1 - 1 2 N - 1 ) respectively.