SLASFL3 September   2026 DAC90802

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Timing Diagrams
    8. 5.8 Typical Characteristics
      1. 5.8.1 Typical Characteristics: Linearity
      2. 5.8.2 Typical Characteristics: Glitch
      3. 5.8.3 Typical Characteristics: Multiplying Mode
      4. 5.8.4 Typical Characteristics: Fast-Settling Mode
      5. 5.8.5 Typical Characteristics: AWG Mode
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Digital-to-Analog Converters
        1. 6.3.1.1 Reference
        2. 6.3.1.2 Output Span
          1. 6.3.1.2.1 Gain Overrange
        3. 6.3.1.3 Output Synchronization
        4. 6.3.1.4 Thermal Sensors
      2. 6.3.2 Power-On
      3. 6.3.3 Serial Data Interface
        1. 6.3.3.1 SPI Configurations
        2. 6.3.3.2 SPI Stream Mode
        3. 6.3.3.3 SPI Daisy Chain Mode
    4. 6.4 Device Functional Modes
      1. 6.4.1 AWG Mode
      2. 6.4.2 Fast Settling Mode
      3. 6.4.3 Multiplying Mode
  8. 7 Register Maps
    1. 7.1 COMMON Registers
    2. 7.2 HS_DATA Registers
    3. 7.3 HR_DATA Registers
  9. 8 Application and Implementation
    1. 8.1 Application
    2. 8.2 Design Requirements
      1. 8.2.1 Reference Signal Chain Information
        1. 8.2.1.1 DC Reference
        2. 8.2.1.2 AC Reference
      2. 8.2.2 Optimising the Self-Heating Trim to Achieve Lowest THD Across Frequencies for High Voltage Swing
      3. 8.2.3 Digital Interface
      4. 8.2.4 Grounding Recommendations
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Recommendation
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

8.4.1 Layout Recommendation

The PCB layout is critical for achieving the specified ac and dc performance of the DAC90802. Although the device is designed to segregate analog, reference, and digital grounds to minimize noise coupling, a simplified layout can still provide excellent results. By utilizing a single ground plane for the reference section and a separate plane for the digital and analog I/O sections connected through a single-point connection as shown in Figure 8-8 adequate performance is achieved while significantly simplifying the design process.

To enhance signal integrity, digital signals and power supplies must be routed in such a way that digital switching noise is prevented from coupling into the sensitive analog signal path.

To achieve the best signal integrity, place all critical components of the signal chain on the top layer with a solid analog ground from subsequent inner layers to minimize loop inductance. For effective power-supply decoupling, position bypass capacitors near the respective power pins. Furthermore, providing unbroken ground return planes beneath the digital signal traces, particularly for high-speed digital signals, minimizes loop inductance and preserves signal quality.

Use X7R 100nF and 1μF capacitors in parallel for decoupling VCC, VEE, DVDD, VIO, and AVDD. For LVDD, an X7R 10μF capacitor is required; placing this capacitor as close as possible to the LVDD and LGND pins is critical to minimizing glitches.

Reference Buffer and Decoupling Placement of the reference buffer near the DAC reference force and sense pins is critical. A 100pF bypass capacitor (recommended specifically for dc applications) placed directly between the force and sense pins with minimal trace length minimizes parasitic impedance. This configuration provides local charge storage for transient reference currents during DAC switching and allows the sense connection to accurately track the reference voltage at the DAC input, improving overall system dynamic performance.

Provide thermal relief (must be connected to VEE) in the bottom layer with an area > 2in2 for best thermal performance.