SLASFL3 September   2026 DAC90802

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Timing Diagrams
    8. 5.8 Typical Characteristics
      1. 5.8.1 Typical Characteristics: Linearity
      2. 5.8.2 Typical Characteristics: Glitch
      3. 5.8.3 Typical Characteristics: Multiplying Mode
      4. 5.8.4 Typical Characteristics: Fast-Settling Mode
      5. 5.8.5 Typical Characteristics: AWG Mode
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Digital-to-Analog Converters
        1. 6.3.1.1 Reference
        2. 6.3.1.2 Output Span
          1. 6.3.1.2.1 Gain Overrange
        3. 6.3.1.3 Output Synchronization
        4. 6.3.1.4 Thermal Sensors
      2. 6.3.2 Power-On
      3. 6.3.3 Serial Data Interface
        1. 6.3.3.1 SPI Configurations
        2. 6.3.3.2 SPI Stream Mode
        3. 6.3.3.3 SPI Daisy Chain Mode
    4. 6.4 Device Functional Modes
      1. 6.4.1 AWG Mode
      2. 6.4.2 Fast Settling Mode
      3. 6.4.3 Multiplying Mode
  8. 7 Register Maps
    1. 7.1 COMMON Registers
    2. 7.2 HS_DATA Registers
    3. 7.3 HR_DATA Registers
  9. 8 Application and Implementation
    1. 8.1 Application
    2. 8.2 Design Requirements
      1. 8.2.1 Reference Signal Chain Information
        1. 8.2.1.1 DC Reference
        2. 8.2.1.2 AC Reference
      2. 8.2.2 Optimising the Self-Heating Trim to Achieve Lowest THD Across Frequencies for High Voltage Swing
      3. 8.2.3 Digital Interface
      4. 8.2.4 Grounding Recommendations
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Recommendation
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

7.2 HS_DATA Registers

Table 7-10 lists the memory-mapped registers for the HS_DATA registers. All register offset addresses not listed in Table 7-10 should be considered as reserved locations and the register contents should not be modified.

Table 7-10 HS_DATA Registers
AddressAcronymBit 15Bit 14Bit 13Bit 12Bit 11Bit 10Bit 9Bit 8
Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
0x60CH0_DATA_HSCH0_DATA_HS
CH0_DATA_HS
0x61CH1_DATA_HSCH1_DATA_HS
CH1_DATA_HS

Complex bit access types are encoded to fit into small table cells. Table 7-11 shows the codes that are used for access types in this section.

Table 7-11 HS_DATA Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

7.2.1 CH0_DATA_HS Register (Address = 0x60) [Reset = 0x0000]

Return to the Summary Table.

Table 7-12 CH0_DATA_HS Register Field Descriptions
BitFieldTypeResetDescription
15-0CH0_DATA_HSR/W0x0 High speed DAC data register for channel 0.
Data word is 16-b wide, MSB aligned, QSPI input with optional stream mode support.

7.2.2 CH1_DATA_HS Register (Address = 0x61) [Reset = 0x0000]

Return to the Summary Table.

Table 7-13 CH1_DATA_HS Register Field Descriptions
BitFieldTypeResetDescription
15-0CH1_DATA_HSR/W0x0 High speed DAC data register for channel 1.
Data word is 16-b wide, MSB aligned, QSPI input with optional stream mode support.