SLASFL3 September   2026 DAC90802

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Timing Diagrams
    8. 5.8 Typical Characteristics
      1. 5.8.1 Typical Characteristics: Linearity
      2. 5.8.2 Typical Characteristics: Glitch
      3. 5.8.3 Typical Characteristics: Multiplying Mode
      4. 5.8.4 Typical Characteristics: Fast-Settling Mode
      5. 5.8.5 Typical Characteristics: AWG Mode
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Digital-to-Analog Converters
        1. 6.3.1.1 Reference
        2. 6.3.1.2 Output Span
          1. 6.3.1.2.1 Gain Overrange
        3. 6.3.1.3 Output Synchronization
        4. 6.3.1.4 Thermal Sensors
      2. 6.3.2 Power-On
      3. 6.3.3 Serial Data Interface
        1. 6.3.3.1 SPI Configurations
        2. 6.3.3.2 SPI Stream Mode
        3. 6.3.3.3 SPI Daisy Chain Mode
    4. 6.4 Device Functional Modes
      1. 6.4.1 AWG Mode
      2. 6.4.2 Fast Settling Mode
      3. 6.4.3 Multiplying Mode
  8. 7 Register Maps
    1. 7.1 COMMON Registers
    2. 7.2 HS_DATA Registers
    3. 7.3 HR_DATA Registers
  9. 8 Application and Implementation
    1. 8.1 Application
    2. 8.2 Design Requirements
      1. 8.2.1 Reference Signal Chain Information
        1. 8.2.1.1 DC Reference
        2. 8.2.1.2 AC Reference
      2. 8.2.2 Optimising the Self-Heating Trim to Achieve Lowest THD Across Frequencies for High Voltage Swing
      3. 8.2.3 Digital Interface
      4. 8.2.4 Grounding Recommendations
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Recommendation
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

6.3.3.1 SPI Configurations

In the default SPI mode of operation the SPI write of DAC90802 uses a 40-bit data frame for all registers, except for the DAC_DATA_CHx_X registers. The CHx_DATA_HS register uses a 24-bit frame and the CHx_DATA_HR register uses a 32 bit frame. The R/W bit and the seven address bits are followed by either 32, 24 or 16 bits of data. In configurations where data readback is supported, the readback data frame also confirms to the write cycle preceding the readback. In SPI stream mode, the R/W bit and address bits are skipped, allowing faster data transfer to the DACs.

For standard SPI, while using only SDIO0 as input, the frame length options are shown in Figure 6-5, Figure 6-7, and Figure 6-6.

DAC90802 SDR Standard SPI 40 Bits Frame Figure 6-5 SDR Standard SPI 40 Bits Frame
DAC90802 SDR Standard SPI 24 Bits Frame for CHx_DATA_HS Registers Figure 6-6 SDR Standard SPI 24 Bits Frame for CHx_DATA_HS Registers
DAC90802 SDR Standard SPI 32 Bits Frame for CHx_DATA_HR Registers Figure 6-7 SDR Standard SPI 32 Bits Frame for CHx_DATA_HR Registers
The quad-SPI width is also selectable between standard SPI, dual-SPI, and quad-SPI with pin configurations as per Table 6-2. This device supports single or dual data-rate communication including stream mode for data registers in any SPI-width configuration. The default configuration is SDR mode with standard SPI.
Table 6-2 Supported Quad-SPI Pin Widths
SPI Width Mode Standard SPI
(SPI_CFG.SPI_MIO = 0x0)		 Dual SPI
(SPI_CFG.SPI_MIO = 0x1)		 Quad SPI
(SPI_CFG.SPI_MIO = 0x2)
Data Rate Mode
(SPI_CFG.SPI_DDR) 		SDR DDR SDR DDR SDR DDR
Serial Data Inputs SDIO0 only SDIO0, and SDIO1 SDIO0, SDIO1, SDIO2, and SDIO3
Serial Data Outputs SDIO3 only DDR not supported SDIO2 and SDIO3 DDR not Supported Readback not supported
Table 6-3 Supported Data Frame Lengths With Address Bytes
Field Address Bytes Data Bytes Standard SPI Dual SPI Quad SPI
SDR DDR SDR DDR SDR DDR
CHx_DATA_HS 1 2 24 cycles 12 cycles 12 cycles 6 cycles 6 cycles 3 cycles
CHx_DATA_HR 1 3 32 cycles 16 cycles 16 cycles 8 cycles 8 cycles 4 cycles
Others 1 4 40 cycles 20 cycles 20 cycles 10 cycles 10 cycles 5 cycles
DAC90802 SDR Dual-SPI 40-Bit Frame Figure 6-8 SDR Dual-SPI 40-Bit Frame
DAC90802 SDR Quad-SPI 40-Bit Frame Figure 6-9 SDR Quad-SPI 40-Bit Frame