SLASFL3 September   2026 DAC90802

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Timing Diagrams
    8. 5.8 Typical Characteristics
      1. 5.8.1 Typical Characteristics: Linearity
      2. 5.8.2 Typical Characteristics: Glitch
      3. 5.8.3 Typical Characteristics: Multiplying Mode
      4. 5.8.4 Typical Characteristics: Fast-Settling Mode
      5. 5.8.5 Typical Characteristics: AWG Mode
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Digital-to-Analog Converters
        1. 6.3.1.1 Reference
        2. 6.3.1.2 Output Span
          1. 6.3.1.2.1 Gain Overrange
        3. 6.3.1.3 Output Synchronization
        4. 6.3.1.4 Thermal Sensors
      2. 6.3.2 Power-On
      3. 6.3.3 Serial Data Interface
        1. 6.3.3.1 SPI Configurations
        2. 6.3.3.2 SPI Stream Mode
        3. 6.3.3.3 SPI Daisy Chain Mode
    4. 6.4 Device Functional Modes
      1. 6.4.1 AWG Mode
      2. 6.4.2 Fast Settling Mode
      3. 6.4.3 Multiplying Mode
  8. 7 Register Maps
    1. 7.1 COMMON Registers
    2. 7.2 HS_DATA Registers
    3. 7.3 HR_DATA Registers
  9. 8 Application and Implementation
    1. 8.1 Application
    2. 8.2 Design Requirements
      1. 8.2.1 Reference Signal Chain Information
        1. 8.2.1.1 DC Reference
        2. 8.2.1.2 AC Reference
      2. 8.2.2 Optimising the Self-Heating Trim to Achieve Lowest THD Across Frequencies for High Voltage Swing
      3. 8.2.3 Digital Interface
      4. 8.2.4 Grounding Recommendations
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Recommendation
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

5.5 Electrical Characteristics

At TA = –40°C to +100°C, VCC = +8.5V to +23.5V, VEE = –8.5V to –23.5V, AVDD = 5.0V, DVDD = 1.5V, LVDD = 1.5V, VIO = 1.5V, VOSADJ_ENx = 0, OFS_ENx = 0, ROFS_F = ROFS_S = VOSADJ = AGND, see note for VREFPX and VREFNX, all typical values at TA = 25°C, output unloaded (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
STATIC PERFORMANCE (DAC_CONFIG_CHx = 01h)
N Resolution 18 Bits
INL Relative accuracy Bipolar, VREFP = 5V and VREFN = –5V, gain = 1 × –1.9 1.9 ppm
Bipolar, VREFP = 5V and VREFN = –5V, gain = 2 × –3.8 3.8
Bipolar, VREFP = 5V and VREFN = –5V, gain = 4 × –9.5 9.5
Bipolar, VREFP = 20V and VREFN = –20V, gain = 1 × –9.5 9.5
Unipolar, VREFP = 0V and VREFN = –5V, gain = 1 × –3.8 3.8
Unipolar, VREFP = 0V and VREFN = –5V, gain = 4 × –11.4 11.4
Unipolar, VREFP = 0V and VREFN = –20V, gain = 1 × –11.4 11.4
Unipolar, VREFP = 0V and VREFN = –5V, gain = 2 × –3.8 3.8
Relative accuracy drift over time TA = 25°C, 1000 hours ±0.07 ppm
TA = 50°C, 1000 hours ±0.07
DNL Differential nonlinearity Bipolar, VREFP = 5V and VREFN = –5V,
gain = 1 ×, 2 ×, 4 ×		 –1.9 1.9 ppm
Unipolar, VREFP = 0V and VREFN = –5V,
gain = 1 ×, 2 ×, 4 ×		 –2.3 2.3
Bipolar, VREFP = 20V and VREFN = –20V, gain = 1 × –3.8 3.8
Unipolar, VREFP = 0V and VREFN = –20V, gain = 1 × –3.8 3.8
GOV Gain over-range For system calibration 2 %
GETC Gain-error temperature coefficient –1.5 ppm FSR/°C
Zero-code error Unipolar, VREFP = 0V, VREFN = –5V, gain = 1 × –84 84 ppm
Unipolar, VREFP = 0V, VREFN = –5V, gain = 2 × –70 70
Unipolar, VREFP = 0V, VREFN = –5V, gain = 4 × –65 65
Unipolar, VREFP = 0V, VREFN = –20V, gain = 1 × –38 38
Midcode error Bipolar, VREFP = 5V, VREFN = –5V,
gain = 1 ×, 2 ×, 4 ×		 –75 75 ppm
Bipolar, VREFP = 10V, VREFN = –10V,
gain = 1 ×, 2 ×		 –75 75
Bipolar, VREFP = 20V, VREFN = –20V, gain = 1 × –75 75
Gain error Bipolar, VREFP = 5V, VREFN = –5V, gain = 1 × –210 210 ppm
Bipolar, VREFP = 10V, VREFN = –10V, gain = 1 × –210 210
Bipolar, VREFP = 7.6V, VREFN = –7.6V, gain = 2 × –400 400
Bipolar, VREFP = 20V, VREFN = –20V, gain = 1 × –350 350
Bipolar, VREFP = 5V, VREFN = –5V, gain = 4 × –450 450
Unipolar, VREFP = 0V, VREFN = –5V, gain = 1 × –250 250
Unipolar, VREFP = 0V, VREFN = –10V, gain = 1 × –250 250
Unipolar, VREFP = 0V, VREFN = –7.6V, gain = 2 × –400 400
Unipolar, VREFP = 0V, VREFN = –20V, gain = 1 × –350 350
Unipolar, VREFP = 0V, VREFN = –5V, gain = 4 × –450 450
Zero-code-error temperature drift Unipolar, VREFP = 0V, VREFN = –5V, gain = 1 × 2 µV/C
Unipolar, VREFP = 0V, VREFN = –5V, gain = 2 × 3.5
Unipolar, VREFP = 0V, VREFN = –5V, gain = 4 × 6.5
Unipolar,VREFP = 0V, VREFN = –20V, gain = 1 × 3.5
Midcode-error temperature drift Bipolar, VREFP = 5V, VREFN = –5V, gain = 1 × 3 µV/C
Bipolar, VREFP = 5V, VREFN = –5V, gain = 4 × 10
Bipolar, VREFP = 20V, VREFN = –20V, gain = 1 × 8.5
Bipolar, VREFP = 5V, VREFN = –5V, gain = 2 × 5.5
LTD Output-voltage-drift over time TA = 25°C, VOUT = midscale, 1000 hours 1 ppm
TA = 50°C, VOUT = midscale, 1000 hours 1
INTEGRATED RESISTORS
R1 Reference-inversion resistor 4 kΩ
R2 Reference-inversion resistor 4 kΩ
R1/R2 Inversion-resistor-ratio mismatch 200 ppm
ΔR1/R2 Inversion-resistor-ratio-mismatch drift 0.6 ppm/C
ROFS Coarse-offset resistor 8 kΩ
ROSADJ Fine-offset-adjust resistor 512 kΩ
RFB Feedback resistor Gain = 1 × 4 kΩ
Gain = 2 × 8 kΩ
Gain = 4 × 16 kΩ
OUTPUT CHARACTERISTICS
Headroom(1) From VOUT to VCC pins 3 V
From VOUT to VEE pins –3
VOUT Output-voltage span Range for VOUT and RFB –20.5 20.5 V
PSRR Power-supply-rejection ratio (dc) VCC = 22V ±1.5V VEE = –23.5V –105 dB
VCC = 23.5V , VEE = –22 V ±1.5V –105 dB
AVDD = 5V ± 0.5V –105 dB
LVDD = 1.5V ± 0.15V –85 dB
CL Output capacitive load(1) AWG mode (DAC_CONFIG_CHx = 00h) 25 pF
Fast-settling mode (DAC_CONFIG_CHx = 01h),
Multiplying mode (DAC_CONFIG_CHx = 02h)		 35
ISCVOUT Output short-circuit current VOUT pin 80 135 mA
REFERENCE INPUTS
IREFP Reference-input current VREFP pin (excludes R1, R2 connections) 9.5 mA
IREFN VREFN pin (excludes R1, R2 connections) –9.5
CVREF Input-capacitance to AGND 10 pF
VREF DC reference-voltage functional range(2) VREFN and VREFP pins –21 21 V
VREFIN REFIN-pin voltage range(2) VREFIN relative to AGND –21 21 V
VOFFSET VOSADJ and ROFS pin DC Offset voltage range(2) VOSADJ and VROFS relative to AGND –21 21 V
DYNAMIC PERFORMANCE - AWG MODE (DAC_CONFIG_CHx = 00h)
THD Total harmonic distortion fOUT = 2kHz full-scale sine wave,
fs = 5MHz, VREFP = 5V, VREFN = –5V, gain = 1 ×		 –125 dB
fOUT = 20kHz full-scale sine wave,
fs = 5MHz, VREFP = 5V, VREFN = –5V, gain = 1 ×		 –120
fOUT = 100kHz full-scale sine wave,
fs = 5MHz, VREFP = 5V, VREFN = –5V, gain = 1 ×		 –110
SNR Signal-to-noise ratio 0.1Hz to 20kHz, fOUT = 2kHz full-scale sine wave,
fs = 5MHz, VREFP = 5V, VREFN = –5V, gain = 1 ×		 122 dB
0.1Hz to 250kHz, fOUT = 20kHz full-scale sine wave,
fs = 5MHz, VREFP = 5V, VREFN = –5V, gain = 1 ×		 112
0.1Hz to 500kHz, fOUT = 100kHz full-scale sine wave,
fs = 5MHz, VREFP = 5V, VREFN = –5V, gain = 1 ×		 110
ts Output-voltage settling time 100mV output settling to ±0.0004%,
VREFP = 7.6V, VREFN = –7.6V, gain = 1 ×		 455 ns
100mV output settling to ±0.0004%,
VREFP = 5V, VREFN = –5V, gain = 1 ×		 500
100mV output settling to ±0.0004%,
VREFP = 5V, VREFN = –5V, gain = 2 ×		 450
100mV output settling to ±0.0004%,
VREFP = 5V, VREFN = –5V, gain = 4 ×		 528
100mV output settling to ±0.0004%,
VREFP = 20V, VREFN = –20V, gain = 1 ×		 420
SR Slew rate Full-scale step, measured at VOUT pin, VREFP = 5V, VREFN = –5V, gain = 1 × 70 V/µs
Full-scale step, measured at VOUT pin, VREFP = 5V, VREFN = –5V, gain = 4 × 160
Full-scale step, measured at VOUT pin, VREFP = 20V, VREFN = –20V, gain = 1 × 192
DYNAMIC PERFORMANCE - FAST SETTLING MODE (DAC_CONFIG_CHx = 01h)
Overshoot 0mV to 100mV output step 2 %
0V to 10V output step 2
ts Output-voltage settling time 100mV output settling to 0.1%FSR,
VREFP = 5V, VREFN = –5V, gain = 1 ×		 52 ns
Full-scale output settling to 0.1%FSR,
VREFP = 5V, VREFN = –5 V, gain = 1 ×		 226
200mV output settling to 0.1%FSR,
VREFP = 5V, VREFN = –5V, gain = 2 ×		 66
Full-scale output settling to 0.1%FSR,
VREFP = 5V, VREFN = –5V, gain = 2 ×		 288
400mV output settling to 0.1%FSR,
VREFP = 5V, VREFN = –5V, Gain = 4 ×		 96
Full-scale output settling to 0.1%FSR,
VREFP = 5V, VREFN = –5V, gain = 4 ×		 450
100mV output settling to 0.1%FSR,
VREFP = 20V, VREFN = –20V, gain = 1 ×		 49
Full-scale output settling to 0.1%FSR,
VREFP = 20V, VREFN = –20V, gain = 1 ×		 290
ts Output-voltage settling time 100mV settling to ±0.0004%,
VREFP = 5V, VREFN = –5V, gain = 1 ×		 178 ns
Full-scale settling to ±0.0004%,
VREFP = 5V, VREFN = –5V, gain = 1 ×		 385
100mV settling to ±0.0004%,
VREFP = 5V, VREFN = –5V, gain = 2 ×		 167
Full-scale settling to ±0.0004%,
VREFP = 5V, VREFN = –5V, gain = 2 ×		 1500
100mV settling to ±0.0004%,
VREFP = 5V, VREFN = –5V, gain = 4 ×		 237
Full-scale settling to ±0.0004%,
VREFP = 5V, VREFN = –5V, gain = 4 ×		 1903
100mV settling to ±0.0004%,
VREFP = 20V, VREFN = –20V, gain = 1 ×		 154
Full-scale settling to ±0.0004%,
VREFP = 20V, VREFN = –20V, gain = 1 ×		 920
Power-on glitch magnitude Measured at DAC voltage output on channel power up 1 V
Channel power-on time(1) Measured at DAC voltage output on channel power up 400 µs
Code-change glitch impulse, absolute integral(3) Midscale LSB transition at –5V to +5V range,
gain = 1 ×, integrated over LDAC edge to settling time (ts)		 140 pV-s
Code-change glitch impulse, direct integral(4) Midscale LSB transition at –5V to +5V range,
gain = 1 ×, integrated over LDAC edge to settling time (ts)		 32
Code-change glitch impulse voltage Midscale LSB transition at –5V to +5V range,
gain = 1 ×		 9 mV
SR Slew rate Full-scale step, measured at VOUT pin, VREFP = 5V, VREFN = –5V, gain = 1 × 145 V/µs
Full-scale step, measured at VOUT pin, VREFP = 5V, VREFN = –5V, gain = 4 × 188
Full-scale step, measured at VOUT pin, VREFP = 20V, VREFN = –20V. gain = 1 × 217
Digital feedthrough
(absolute Integral)		 Gain = 1 ×, SCLK = 1MHz, all other digital lines are static 15 pV-s
DYNAMIC PERFORMANCE - MULTIPLYING MODE (DAC_CONFIG_CHx = 02h)
VREF AC reference voltage range Input on VREFN, VREFP = REFGND –21 21 V
MBW Reference-multiplying bandwidth VREFP = 0V and VREFIN = ±100mV, gain = 1 ×, full scale 25 MHz
VREFP = 0V and VREFIN = ±5V, gain = 1 ×, full scale 9
VREFP = 0V and VREFIN = ±5V, gain = 4 ×, full scale 2.5
VREFP = 0V and VREFIN = ±20V, gain = 1 ×, full scale 3
MFE Multiplying feedthrough error Gain = 4 ×, zero scale, 100kHz, VREFP = 0V, VREFIN = ±5V –80 dB
Gain = 1 ×, zero scale, 100kHz, VREFP = 0V, VREFIN = 100mVRMS –90
Gain = 1 ×, zero scale, 100kHz, VREFP = 0V, VREFIN = ±20V –90
THDM Multiplying THD fIN = 2 kHz at VREFP = 0, VREFIN = ±5 V, gain = 1 × –124 dB
fIN = 20 kHz at VREFP = 0, VREFIN = ±5 V, gain = 1 × –120
fIN = 100kHz at VREFP = 0V, VREFIN = ±5V, gain = 1 × –108
SR Slew rate Full-scale step, measured at VOUT pin, VREFP = 5V, VREFN = –5V, gain = 1 × 122 V/µs
Full-scale step, measured at VOUT pin, VREFP = 5V, VREFN = –5V, gain = 4 × 112
Full-scale step, measured at VOUT pin, VREFP = 20V, VREFN = –20V, gain = 1 × 194
NOISE PERFORMANCE (DAC_CONFIG_CHx = 01h)
Vn Output noise 0.1Hz to 10Hz, gain = 1 × 6 µVPP
0.1Hz to 10Hz, gain = 4 × 16
1/f Noise corner frequency Gain = 1 × 680 Hz
Gain = 4 × 580
Output noise density Measured at 10kHz, gain = 1 × (excluding R1, R2) 17 nV/√Hz
Measured at 10kHz, gain = 4 × (excluding R1, R2) 52
Power-supply-rejection ratio (ac) 200mVPP, 50Hz or 60Hz sine wave superimposed on VCC, VCC = 23.4V, VEE = –23.5V, AVDD = 5V,
LVDD = 1.5V		 –100 dB
200mVPP, 50Hz or 60Hz sine wave superimposed on VEE, VCC = 23.5V, VEE = –23.4V, AVDD = 5V,
LVDD = 1.5V		 –100
200mVPP, 50Hz or 60Hz sine wave superimposed on AVDD, VCC = 23.5V, VEE = –23.5V, AVDD = 5V,
LVDD = 1.5V		 –96
50mVPP, 50Hz or 60Hz sine wave superimposed on LVDD, VCC = 23.5V, VEE = –23.5V, AVDD = 5V,
LVDD = 1.5V, gain = 1 ×		 –90
50mVPP, 50Hz or 60Hz sine wave superimposed on LVDD, VCC = 23.5V, VEE = –23.5V, AVDD = 5V,
LVDD = 1.5V, gain = 4 ×		 –80
TEMPERATURE SENSOR ANALOG OUTPUT MODE
Temperature sensing range TEMP analog output mode –40 150 ℃
VTEMP25 Output voltage TJ = 25℃ 1.8 V
GTEMP Sensor gain 20 mV/℃
VTEMP Output voltage span 0.5 4.3 V
Absolute accuracy ±5 ℃
ZOATEMP TEMP signal output impedance 0.85 kΩ
TEMPERATURE SENSOR DIGITAL OUTPUT MODE
TOSD Over temperature shutdown threshold range Measured at the junction 29.6 150 ℃
VOLTEMP Low-level output voltage Into high-impedance digital buffer 0.4 V
VOHTEMP High-level output voltage Into high-impedance digital buffer (VIO – 0.4) V
ZODTEMP TEMP signal output impedance 5 kΩ
DIGITAL INPUTS
VIL Low-level input voltage 0.3 V/VIO
VIH High-level input voltage 0.7 V/VIO
VHYS Hysteresis voltage VIO = 1.8V 0.12 V
Input current ±1 µA
Pin capacitance Per pin 2 pF
DIGITAL OUTPUTS
VOL Low-level output voltage Sinking 200µA 0.4 V
VOH High-level output voltage Sourcing 200µA (VIO – 0.4) V
IOZ High-impedance leakage ±1 µA
COZ High-impedance output capacitance 2 pF
SPI
fSPI SPI Frequency 66 MHz
DAC update rate DDR enabled,16-bit mode, 66MHz SCLK, SDIO0 through SDIO3 as inputs, single channel stream mode 33 MUPS
DDR enabled, 18-bit mode, 66MHz SCLK, SDIO0 through SDIO3 as inputs, single channel stream mode, 22
DDR disabled, 16-bit mode, 66MHz SCLK, SDIO0 through SDIO3 as inputs, single channel stream mode 16.5
DDR disabled, 18-bit mode, 66MHz SCLK, SDIO0 through SDIO3 as inputs, single channel stream mode 11
Daisy chain mode (DDR disabled), 66MHz SCLK, SDIO0 and SDIO1 as SDI, SDIO2 and SDIO3 as SDO, single secondary SPI 3.3
POWER
IVCC_S Standby-mode rail current VCC = 23.5V, VEE = –23.5V, AVDD = 5.4V, DVDD = 1.65V, LVDD = 1.65V 0.16 mA
IVEE_S Standby-mode rail current VCC = 23.5V, VEE = –23.5V, AVDD = 5.4V, DVDD = 1.65V, LVDD = 1.65V –0.16 mA
IAVDD_S Standby-mode rail current VCC = 23.5V, VEE = –23.5V, AVDD = 5.4V, DVDD = 1.65V, LVDD = 1.65V 34 uA
ILVDD_S Standby-mode rail current VCC = 23.5V, VEE = –23.5V, AVDD = 5.4V, DVDD = 1.65V, LVDD = 1.65V 10 uA
IDVDD_S Standby-mode rail current VCC = 23.5V, VEE = –23.5V, AVDD = 5.4V, DVDD = 1.65V, LVDD = 1.65V 15 uA
IAVDD Current flowing into AVDD VREFP = 20V, VREFN = –20V, full scale 2.5 mA
IVCC Current flowing into VCC VREFP = 20V, VREFN = –20V,full scale 30 mA
IVEE Current flowing into VEE VREFP = 20V, VREFN = –20V, zero scale –30 mA
IDVDD Current flowing into DVDD VREFP = 20V, VREFN = –20V, full scale 20 uA
IIOVDD Current flowing into VIO VREFP = 20V, VREFN = –20V, full scale code, all digital input pins static at VIO 10 uA
(1) Guaranteed by design or characterization. Not production tested.
(2) Excludes required headroom.
(3) Absolute integral refers to integrating the absolute magnitude of the glitch waveform to arrive at the glitch energy.
(4) Direct integral refers to integrating the signed magnitude of the glitch waveform to arrive at the glitch energy.