MSP-FET430PIF, MSP-FET430UIF, MSP-GANG, MSP-GANG430, MSP-PRGS430

With the proper connections, the debugger and an FET hardware JTAG interface (such as the MSP-FET430PIF and MSP-FET430UIF) can be used to program and debug code on the target board. In addition, the connections also support the MSP-GANG430 or MSP-PRGS430 production programmers, thus providing an easy way to program prototype boards, if desired.

Figure 3-1 shows the connections between the 14-pin FET interface module connector and the target device required to support in-system programming and debugging for 4-wire JTAG communication. Figure 3-2 shows the connections for 2-wire JTAG mode (Spy-Bi-Wire). The 4-wire JTAG mode is supported on most MSP430 devices, except devices with low pin counts (for example, MSP430G2230). The 2-wire JTAG mode is available on selected devices only. See the Code Composer Studio IDE for MSP430 MCUs User's Guide or IAR Embedded Workbench IDE for MSP430 MCUs User's Guide for information on which interface method can be used on which device.

The connections for the FET interface module and the MSP-GANG, MSP-GANG430, or MSP-PRGS430 are identical. Both the FET interface module and MSP-GANG430 can supply V_CC to the target board (through pin 2). In addition, the FET interface module, MSP-GANG, and MSP-GANG430 have a V_CC-sense feature that, if used, requires an alternate connection (pin 4 instead of pin 2). The V_CC-sense feature senses the local V_CC present on the target board (that is, a battery or other local power supply) and adjusts the output signals accordingly. If the target board is to be powered by a local V_CC, then the connection to pin 4 on the JTAG should be made, and not the connection to pin 2. This uses the V_CC-sense feature and prevents any contention that might occur if the local on-board V_CC were connected to the V_CC supplied from the FET interface module, MSP-GANG or the MSP-GANG430. If the V_CC-sense feature is not necessary (that is, if the target board is to be powered from the FET interface module, MSP-GANG, or MSP-GANG430), the V_CC connection is made to pin 2 on the JTAG header, and no connection is made to pin 4. Figure 3-1 and Figure 3-2 show a jumper block that supports both scenarios of supplying V_CC to the target board. If this flexibility is not required, the desired V_CC connections may be hard-wired to eliminate the jumper block. Pins 2 and 4 must not be connected at the same time.

The connection to the JTAG connector RST pin of Figure 3-1 is required when programming or debugging a device that supports 2-wire JTAG communication, even when using 4-wire JTAG communication mode on these devices. However, this connection is optional on devices that do not support 2-wire JTAG communication. The MSP430 development tools and device programmers perform a target reset by issuing a JTAG command to gain control over the device. However, if this is unsuccessful, the RST signal of the JTAG connector may be used by the development tool or device programmer as an additional way to assert a device reset.

If a local target power supply is used, make connection J1. If power from the debug or programming adapter is used, make connection J2.

The configuration of R1 and C1 for the RST/NMI pin depends on the device family. See the respective MSP430 family user's guide for the recommended configuration.

The TEST pin is available only on MSP430 family members with multiplexed JTAG pins. See the device-specific data sheet to determine if this pin is available.

The connection to the JTAG connector RST pin is required when programming or debugging a device that supports 2-wire JTAG communication, even when using 4-wire JTAG communication mode on these devices. However, this connection is optional on devices that do not support 2-wire JTAG communication.

When using a device that supports 2-wire JTAG communication in 4-wire JTAG mode, the upper limit for C1 should not exceed 2.2 nF. The typical value for SBW communication is shown. The range can vary between 0.1 nF and 2.2 nF depending on SBW speed, voltage, and board design. See the device-specific data sheet for device-specific recommendations.

For applications that are particularly concerned with excessive noise or ESD, a 500-Ω to 1-kΩ pulldown resistor can be added to the TEST pin, while still allowing proper programming of the target device.

Figure 2-1 Signal Connections for 4-Wire JTAG Communication

If a local target power supply is used, make connection J1. If power from the debug or programming adapter is used, make connection J2.

The device RST/NMI/SBWTDIO pin is used in 2-wire mode for bidirectional communication with the device during JTAG access, and any capacitance that is attached to this signal can affect the ability to establish a connection with the device. The upper limit for C1 is 2.2 nF when using current TI tools. The typical value for SBW communication is shown. The range can vary between 0.1 nF and 2.2 nF depending on SBW speed, voltage, and board design. See the device-specific data sheet for device-specific recommendations.

R2 protects the JTAG debug interface TCK signal from the JTAG security fuse blow voltage that is supplied by the TEST/VPP pin during the fuse blow process. If fuse blow functionality is not needed, R2 is not required (populate 0 Ω) and do not connect TEST/VPP to TEST/SBWTCK.

For applications that are particularly concerned with excessive noise or ESD, a 500-Ω to 1-kΩ pulldown resistor can be added to the TEST pin, while still allowing proper programming of the target device.

Figure 2-2 Signal Connections for 2-Wire JTAG Communication (Spy-Bi-Wire) Used by MSP430F2xx, MSP430G2xx, and MSP430F4xx Devices

Make connection J1 if a local target power supply is used, or make connection J2 if the target is powered from the debug or programming adapter.

The device RST/NMI/SBWTDIO pin is used in 2-wire mode for bidirectional communication with the device during JTAG access, and any capacitance that is attached to this signal can affect the ability to establish a connection with the device. The upper limit for C1 is 2.2 nF when using current TI tools. The typical value for SBW communication is shown. The range can vary between 0.1 nF and 2.2 nF depending on SBW speed, voltage, and board design. See the device-specific data sheet for device-specific recommendations.

For applications that are particularly concerned with excessive noise or ESD, a 500-Ω to 1-kΩ pulldown resistor can be added to the TEST pin, while still allowing proper programming of the target device.

Figure 2-3 Signal Connections for 2-Wire JTAG Communication (Spy-Bi-Wire) Used by All MSP430 SBW-Capable Devices That are Not Part of F2xx, G2xx, F4xx Families