UVLO is a key gate driver feature that protects the SiC MOSFET by turning off the gate driver output when the bias supply voltage is less than expected. If the bias supply of the gate driver without UVLO drops to a lower voltage, then the gate driver outputs a voltage that can still reach the SiC MOSFET gate-source voltage (V_GS) turn-on threshold, but this results in severe conduction losses because the SiC MOSFET is not fully turned on.

This conduction loss can be shown by the I-V curve relationship between drain current (I_D) and drain-source voltage (V_DS) of a SiC MOSFET, relative to V_GS. A low V_GS can cause the SiC MOSFET to saturate sooner and prevent the MOSFET from fully turning on due to high drain-source on-resistance (R_DS(on)).

Figure 3-1 shows the typical I-V curves for Si MOSFET vs. SiC MOSFET; if the V_GS is lower, then the MOSFET saturates faster. For both Si MOSFET and SiC MOSFET, there are large margins between each curve for V_GS < 10V, indicating that the MOSFET is not fully turned on. Lower V_GS results in higher conduction losses due to higher R_DS(on).

However, the difference between Si MOSFET and SiC MOSFET is more clear for V_GS ≥ 10V. For Si MOSFET, the curves at V_GS = 10V and V_GS = 15V are nearly identical, indicating that the Si MOSFET has fully turned on at V_GS = 10V. Increasing V_GS for Si MOSFET beyond 10V will have minimal effect in reducing conduction losses. For SiC MOSFET, there are still large margins between the curves at V_GS = 10V and V_GS = 15V, indicating that the SiC MOSFET has not fully turned on at V_GS = 10V like its Si MOSFET counterpart. Operating the SiC MOSFET at V_GS = 10V results in more conduction loss when compared to operating at V_GS = 15V.

As a result, high UVLO is often a requirement for SiC MOSFETs to minimize conduction losses during bias supply start-up or shutdown.