SLUAAY0 September   2025 UCC57102 , UCC57102-Q1 , UCC57102Z , UCC57102Z-Q1 , UCC57108 , UCC57108-Q1 , UCC57132 , UCC57132-Q1 , UCC57138 , UCC57138-Q1 , UCC57142 , UCC57142-Q1 , UCC57148 , UCC57148-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2TI Non-Isolated SiC MOSFET Gate Drivers Overview
  6. 3SiC MOSFET Gate Driver Design Considerations
    1. 3.1 Undervoltage Lockout (UVLO)
    2. 3.2 Negative Bias Supply (Bipolar Drive)
    3. 3.3 Short-Circuit Protection
      1. 3.3.1 Desaturation Protection
      2. 3.3.2 Overcurrent Protection
      3. 3.3.3 Soft Turn-Off
  7. 4PFC CCM Boost Low-Side Gate Driver Example
    1. 4.1 Gate Driver Requirements
    2. 4.2 Gate Driver Selection
    3. 4.3 Gate Driver Power Dissipation
  8. 5Summary
  9. 6References

4.1 Gate Driver Requirements

Choosing the proper gate driver for a SiC MOSFET involves careful consideration of the bias voltage rating, peak current capability, protection features, gate resistor, and power dissipation.

To minimize conduction loss, the bias voltage is set to 20V, and a negative bias of -5V is set to prevent accidental turn-on from transients. The potential difference yields the VDD requirement for the gate driver to be at least 25V.

To minimize switching loss, the gate driver must also be capable of providing the required peak current to achieve the target switching speed. The system requirement for switching speed is typically described in terms of slew rate. For the PFC in this example, the requirements state that the SiC MOSFET needs to be turned on with a slew rate of 20V/ns or higher under a DC bus voltage of 400V. This means that the full VDS swing during the SiC MOSFET turn-on needs to occur in 20ns ( = 400 V / 20 V n s ) or less. During VDS swing, the Miller charge of the SiC MOSFET (QGD parameter, which is 27nC for the chosen SiC MOSFET) is charged by the peak current of the gate driver; the peak current needs to charge the QGD in 20ns or less. This yields the required peak current to be at least 1.35A ( = 27 n C / 20 n s ) .

UVLO is a key protection feature to minimize damage to the SiC MOSFET in case of a power supply failure. If a failure causes VGS to fall to unsafe levels, then the SiC MOSFET can experience conduction losses. This can diminish efficiency, increase heating, and reduce lifetime of the SiC MOSFET. A gate driver with a high UVLO rating is beneficial in this application.

Having a form of short-circuit detection is another important protection feature for the SiC MOSFET. Since SiC MOSFETs do not have a clear transition from linear to saturation region like the transition from saturation to active region in IGBTs, using a single-voltage threshold detection such as DESAT protection cannot be accurate without extensive modification. OCP is a more preferred choice, which uses a shunt resistor to measure current.