SLUAAY0 September   2025 UCC57102 , UCC57102-Q1 , UCC57102Z , UCC57102Z-Q1 , UCC57108 , UCC57108-Q1 , UCC57132 , UCC57132-Q1 , UCC57138 , UCC57138-Q1 , UCC57142 , UCC57142-Q1 , UCC57148 , UCC57148-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2TI Non-Isolated SiC MOSFET Gate Drivers Overview
  6. 3SiC MOSFET Gate Driver Design Considerations
    1. 3.1 Undervoltage Lockout (UVLO)
    2. 3.2 Negative Bias Supply (Bipolar Drive)
    3. 3.3 Short-Circuit Protection
      1. 3.3.1 Desaturation Protection
      2. 3.3.2 Overcurrent Protection
      3. 3.3.3 Soft Turn-Off
  7. 4PFC CCM Boost Low-Side Gate Driver Example
    1. 4.1 Gate Driver Requirements
    2. 4.2 Gate Driver Selection
    3. 4.3 Gate Driver Power Dissipation
  8. 5Summary
  9. 6References

4.3 Gate Driver Power Dissipation

Check if the power dissipation of the selected gate driver is within specifications. The total power dissipation (Ptot) in a low side gate driver can be broken down into two portions: DC losses and switching losses. DC losses (PDC) are a function of the gate driver’s quiescent current consumed to bias the internal circuits. The switching losses (PSW) depend on the gate charge, bias voltage, switching frequency, and internal/external gate resistance of the power switch.

The thermal specifications found in the gate driver data sheet and estimated ambient temperature can be used to estimate the maximum allowable power dissipation of the gate driver (Pmax). Pmax can be compared to the calculated Ptot to make sure the gate driver is within specifications. Equation 5 and Equation 6 estimates the maximum power dissipation for the UCC57132B.

Equation 5. P m a x = T J - T A R θ J A
Equation 6. P m a x = 150 ° C - 100 ° C 126 . 6 ° C W = 395 m W

UCC57132B has a maximum VDD quiescent current of 1.3mA and maximum VEE quiescent current of 1.1mA. With a +20V VDD supply and -5V VEE supply, the DC losses are 31.5mW (=(1.3mA×20V)+(-1.1mA×-5V)).

Switching losses can be estimated using Equation 7 and Equation 8. ROH(eff) represents the effective pull-up resistance of the output structure during output turn-on (1Ω); this is due to the hybrid pull-up structure of the UCC57132B output stage, which contains a pull-up NMOS in parallel with the pull-up PMOS. This is distinct from the ROH parameter in the data sheet, which only represents the pull-up PMOS (using ROH instead of ROH(eff) is okay if overestimation is needed). The ROL refers to the typical pull-down NMOS and can be found in the data sheet (1Ω). RGATE(H) refers to the turn-on external gate resistance, and RGATE(L) refers to the turn-off external gate resistance. RGATE(I) refers to the intrinsic gate resistance of the selected SiC MOSFET (2Ω).

Equation 7. P S W = Q g × ( V D D - V E E ) × f s w × 1 2 R O H ( e f f ) R O H ( e f f ) + R G A T E ( H ) + R G A T E ( I ) + R O L R O L + R G A T E ( L ) + R G A T E ( I )
Equation 8. P S W = 73 n C × ( 20 V - ( - 5 V ) ) × 60 k H z × 1 2 1 Ω 1 Ω + 2 . 2 Ω + 2 Ω + 1 Ω 1 Ω + 1 . 1 Ω + 2 Ω = 23 . 9 m W

The estimated total power dissipated in the package is calculated in Equation 9 and Equation 10.

Equation 9. P t o t = P D C + P S W
Equation 10. P t o t = 31 . 5 m W + 23 . 9 m W = 55 . 4 m W

For initial design purposes, the calculated Ptot is much smaller than the estimated Pmax of the UCC57132B, keeping the device within specifications. Further thermal analysis must be completed throughout the design phase to verify proper cooling. More information about thermal analysis can be found by reading Semiconductor and IC Package Thermal Metrics app note.