SLUSFB5A June   2024  – April 2025 BQ41Z50

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
    1. 4.1 Pin Equivalent Diagrams
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Supply Current
    6. 5.6  Power Supply Control
    7. 5.7  Low Dropout Regulators
    8. 5.8  Internal Oscillators
    9. 5.9  Voltage References
    10. 5.10 Current Wake Detector
    11. 5.11 VC0, VC1, VC2, VC3, VC4, PACK
    12. 5.12 Cell Balancing Support
    13. 5.13 SMBD, SMBC
    14. 5.14 PRES/SHUTDN, DISP
    15. 5.15 ALERT
    16. 5.16 LEDCNTLA, LEDCNTLB, LEDCNTLC
    17. 5.17 Coulomb Counter
    18. 5.18 Coulomb Counter Digital Filter (CC1)
    19. 5.19 Current Measurement Digital Filter (CC2)
    20. 5.20 Analog-to-Digital Converter
    21. 5.21 ADC Digital Filter
    22. 5.22 CHG, DSG High-side NFET Drivers
    23. 5.23 Precharge (PCHG) FET Drive
    24. 5.24 FUSE Drive
    25. 5.25 Internal Temperature Sensor
    26. 5.26 TS1, TS2, TS3, TS4
    27. 5.27 Flash Memory
    28. 5.28 OT, SCD, OCC, OCD1, OCD2 Protection Thresholds (SCOMP)
    29. 5.29 OT, SCD, OCC, OCD1, OCD2 Protection Timing (SCOMP)
    30. 5.30 GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6, GPIO7
    31. 5.31 Elliptical Curve Cryptography (ECC)
    32. 5.32 SMBus Interface Timing
    33. 5.33 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Primary (1st Level) Safety Features
      2. 6.3.2 Secondary (2nd Level) Safety Features
      3. 6.3.3 Charge Control Features
      4. 6.3.4 Gas Gauging
      5. 6.3.5 Lifetime Data Logging Features
      6. 6.3.6 Authentication
      7. 6.3.7 Configuration
        1. 6.3.7.1 Oscillator Function
        2. 6.3.7.2 Real Time Clock
        3. 6.3.7.3 System Present Operation
        4. 6.3.7.4 Emergency Shutdown
        5. 6.3.7.5 2-Series, 3-Series, or 4-Series Cell Configuration
        6. 6.3.7.6 Cell Balancing
        7. 6.3.7.7 LED Display
      8. 6.3.8 Battery Parameter Measurements
        1. 6.3.8.1 Charge and Discharge Counting
        2. 6.3.8.2 Voltage
        3. 6.3.8.3 Current
        4. 6.3.8.4 Temperature
        5. 6.3.8.5 Communications
          1. 6.3.8.5.1 SMBus On and Off State
          2. 6.3.8.5.2 SBS Commands
    4. 6.4 Device Functional Modes
  8. 7 Applications and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 High-Current Path
          1. 7.2.2.1.1 Protection FETs
          2. 7.2.2.1.2 Chemical Fuse
          3. 7.2.2.1.3 Lithium-Ion Cell Connections
          4. 7.2.2.1.4 Sense Resistor
          5. 7.2.2.1.5 ESD Mitigation
        2. 7.2.2.2 Gas Gauge Circuit
          1. 7.2.2.2.1 Coulomb-Counting Interface
          2. 7.2.2.2.2 Low-dropout Regulators (LDOs)
            1. 7.2.2.2.2.1 REG18
            2. 7.2.2.2.2.2 REG135
          3. 7.2.2.2.3 System Present
          4. 7.2.2.2.4 SMBus Communication
          5. 7.2.2.2.5 FUSE Circuitry
        3. 7.2.2.3 Secondary-Current Protection
          1. 7.2.2.3.1 Cell and Battery Inputs
          2. 7.2.2.3.2 External Cell Balancing
          3. 7.2.2.3.3 PACK and FET Control
          4. 7.2.2.3.4 Temperature Measurement
          5. 7.2.2.3.5 LEDs
      3. 7.2.3 Application Curves
    3. 7.3 Configuring Device Firmware
  9. 8 Power Supply Recommendations
  10. 9 Layout
    1. 9.1 Layout Guidelines
      1. 9.1.1 Protector FET Bypass and Pack Terminal Bypass Capacitors
      2. 9.1.2 ESD Spark Gap
    2. 9.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Third-Party Products Disclaimer
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

5.30 GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6, GPIO7

Typical values stated where TA = 25°C and VBAT = 14.4V, Min/Max values stated where TA = –40°C to 85°C and VBAT = 3.0V to 28V (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
GPIO1, GPIO2
VIN Input voltage range GPIO1, GPIO2 –0.2 VREG18 V
VIH High-level input voltage GPIO1, GPIO2 0.7 x VREG18 V
VIL Low-level input voltage GPIO1, GPIO2 0.3 x VREG18 V
VIOHYS(1) Hysteresis of Input GPIO1, GPIO2 75 mV
VOH Output voltage high GPIO1, GPIO2: IOH = –450µA 0.85 × VREG18 V
VOL Output voltage low GPIO1, GPIO2: IOH = 1mA 0.35 V
RPD Internal pull-down resistance GPIO1, GPIO2 15 20 30 kΩ
RPU Internal pull-up resistance GPIO1, GPIO2 15 20 30 kΩ
CI(1) Input capacitance GPIO1, GPIO2 1.5 pF
Ilkg(1) Input leakage current GPIO1, GPIO2 1 2 µA
GPIO3
VIN Input voltage range GPIO3 –0.2 5.5 V
VIH High-level input voltage GPIO3 0.7 x VREG18 V
VIL Low-level input voltage GPIO3 0.3 x VREG18 V
VIOHYS(1) Hysteresis of Input GPIO3 75 mV
VOL Output voltage low GPIO3: IOH = 3mA 0.35 V
RBUSPD Internal weak pull-down resistance GPIO3, Always ON 1 3 5 MΩ
RPD Internal pull-down resistance GPIO3 35 40 50 kΩ
CI (1) Input capacitance GPIO3 1.8 pF
Ilkg(1) Input leakage current GPIO3, including always on RBUSPD pull-down 0.5 2 µA
GPIO4, GPIO5, GPIO6, GPIO7 (GPIO mode enabled, LED mode disabled)
VIN Input voltage range GPIO4, GPIO5, GPIO6, GPIO7: Used as open drain GPIO (internal weak pull-up disabled) –0.2 5.5 V
GPIO4, GPIO5, GPIO6, GPIO7: Used as push-pull GPIO (internal weak pull-up enabled) –0.2 VREG18
VIH High-level input voltage GPIO4, GPIO5, GPIO6, GPIO7 0.7 × VREG18 V
VIL Low-level input voltage GPIO4, GPIO5, GPIO6, GPIO7 0.3 x VREG18 V
VIOHYS(1) Hysteresis of Input GPIO4, GPIO5, GPIO6, GPIO7 75 mV
VOH Output voltage high GPIO4, GPIO5, GPIO6, GPIO7: IOH = –1mA 0.7 × VREG18 V
VOL Output voltage low GPIO4, GPIO5, GPIO6, GPIO7: IOL = 3mA 0.3 × VREG18 V
RWKPD Internal weak pull-down resistance GPIO4, GPIO5, GPIO6, GPIO7 0.8 1 1.2 MΩ
RWKPU Internal weak pull-up resistance GPIO4, GPIO5, GPIO6, GPIO7 0.8 1 1.2 MΩ
CI (1) Input capacitance GPIO4, GPIO5, GPIO6, GPIO7 5 pF
Ilkg(1) Input leakage current GPIO4, GPIO5, GPIO6, GPIO7 1 2 µA
(1) Specified by design. Not production tested