SLUSFB5A June   2024  – April 2025 BQ41Z50

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
    1. 4.1 Pin Equivalent Diagrams
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Supply Current
    6. 5.6  Power Supply Control
    7. 5.7  Low Dropout Regulators
    8. 5.8  Internal Oscillators
    9. 5.9  Voltage References
    10. 5.10 Current Wake Detector
    11. 5.11 VC0, VC1, VC2, VC3, VC4, PACK
    12. 5.12 Cell Balancing Support
    13. 5.13 SMBD, SMBC
    14. 5.14 PRES/SHUTDN, DISP
    15. 5.15 ALERT
    16. 5.16 LEDCNTLA, LEDCNTLB, LEDCNTLC
    17. 5.17 Coulomb Counter
    18. 5.18 Coulomb Counter Digital Filter (CC1)
    19. 5.19 Current Measurement Digital Filter (CC2)
    20. 5.20 Analog-to-Digital Converter
    21. 5.21 ADC Digital Filter
    22. 5.22 CHG, DSG High-side NFET Drivers
    23. 5.23 Precharge (PCHG) FET Drive
    24. 5.24 FUSE Drive
    25. 5.25 Internal Temperature Sensor
    26. 5.26 TS1, TS2, TS3, TS4
    27. 5.27 Flash Memory
    28. 5.28 OT, SCD, OCC, OCD1, OCD2 Protection Thresholds (SCOMP)
    29. 5.29 OT, SCD, OCC, OCD1, OCD2 Protection Timing (SCOMP)
    30. 5.30 GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6, GPIO7
    31. 5.31 Elliptical Curve Cryptography (ECC)
    32. 5.32 SMBus Interface Timing
    33. 5.33 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Primary (1st Level) Safety Features
      2. 6.3.2 Secondary (2nd Level) Safety Features
      3. 6.3.3 Charge Control Features
      4. 6.3.4 Gas Gauging
      5. 6.3.5 Lifetime Data Logging Features
      6. 6.3.6 Authentication
      7. 6.3.7 Configuration
        1. 6.3.7.1 Oscillator Function
        2. 6.3.7.2 Real Time Clock
        3. 6.3.7.3 System Present Operation
        4. 6.3.7.4 Emergency Shutdown
        5. 6.3.7.5 2-Series, 3-Series, or 4-Series Cell Configuration
        6. 6.3.7.6 Cell Balancing
        7. 6.3.7.7 LED Display
      8. 6.3.8 Battery Parameter Measurements
        1. 6.3.8.1 Charge and Discharge Counting
        2. 6.3.8.2 Voltage
        3. 6.3.8.3 Current
        4. 6.3.8.4 Temperature
        5. 6.3.8.5 Communications
          1. 6.3.8.5.1 SMBus On and Off State
          2. 6.3.8.5.2 SBS Commands
    4. 6.4 Device Functional Modes
  8. 7 Applications and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 High-Current Path
          1. 7.2.2.1.1 Protection FETs
          2. 7.2.2.1.2 Chemical Fuse
          3. 7.2.2.1.3 Lithium-Ion Cell Connections
          4. 7.2.2.1.4 Sense Resistor
          5. 7.2.2.1.5 ESD Mitigation
        2. 7.2.2.2 Gas Gauge Circuit
          1. 7.2.2.2.1 Coulomb-Counting Interface
          2. 7.2.2.2.2 Low-dropout Regulators (LDOs)
            1. 7.2.2.2.2.1 REG18
            2. 7.2.2.2.2.2 REG135
          3. 7.2.2.2.3 System Present
          4. 7.2.2.2.4 SMBus Communication
          5. 7.2.2.2.5 FUSE Circuitry
        3. 7.2.2.3 Secondary-Current Protection
          1. 7.2.2.3.1 Cell and Battery Inputs
          2. 7.2.2.3.2 External Cell Balancing
          3. 7.2.2.3.3 PACK and FET Control
          4. 7.2.2.3.4 Temperature Measurement
          5. 7.2.2.3.5 LEDs
      3. 7.2.3 Application Curves
    3. 7.3 Configuring Device Firmware
  9. 8 Power Supply Recommendations
  10. 9 Layout
    1. 9.1 Layout Guidelines
      1. 9.1.1 Protector FET Bypass and Pack Terminal Bypass Capacitors
      2. 9.1.2 ESD Spark Gap
    2. 9.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Third-Party Products Disclaimer
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

5.6 Power Supply Control

Typical values stated where TA = 25°C and VBAT = 14.4V, Min/Max values stated where TA = –40°C to 85°C and VBAT = 3.0V to 28V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Power Selector
VSTARTUP Startup voltage at PACK VPACK > VSTARTUP for 1ms 3.5 4.5 5.5 V
VSWITCHOVER– BAT to VCC switchover voltage VBAT < VSWITCHOVER– 2.5 2.75 3.0 V
VSWITCHOVER+ VCC to BAT switchover voltage VBAT > VSWITCHOVER– + VHYS 3.4 3.85 4.15 V
VHYS Switchover hysteresis voltage VSWITCHOVER+ - VSWITCHOVER– 1.1 V
TSD_ALERT+ Thermal shutdown alert temperature rising 120 135 °C
TSD_ALERT– Thermal shutdown alert temperature falling Exit from RESET, REG135 enabled 100 102 °C
TSD+ Thermal shutdown temperature rising 140 148 °C
TSD– Thermal shutdown temperature falling REG18 Enabled 122 130 °C
ILKG Input leakage current BAT pin, BAT = 0V, VCC = 25V, PACK = 25V 1 µA
PACK pin, BAT = 25V, VCC = 0V, PACK = 0V 1
RPACK_PD Internal pull-down resistance PACK pin 30 40 50 kΩ
Power On Reset
VREG18POR– Negative-going VREG18 output POR voltage VREG18 1.5 1.55 1.60 V
VHYS Power on reset hysteresis 65 85 110 mV
tRST_POR(1) Power on reset time: From application of valid input voltage to release of POR for the MCU 2.5 4.0 ms
tRST_ROM(1) Power on reset time: From application of valid input voltage to CPU ready to execute ROM code 5 10 ms
tRST_EXE(1) Power on reset time: From application of valid input voltage to CPU ready to execute flash code Not including CRC of flash array performed by ROM 5 10 ms
(1) Specified by design. Not production tested