SLUUDB4 June   2025 TAS5830

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1General Overview
    1. 1.1 Supported Use Cases
  5. 2Process Flows
    1. 2.1  Overview
    2. 2.2  Process Flow 1
      1. 2.2.1  SRC
      2. 2.2.2  Input Mixer
      3. 2.2.3  Equalizer
      4. 2.2.4  Volume
      5. 2.2.5  DPEQ
      6. 2.2.6  3-Band DRC
      7. 2.2.7  AGL
      8. 2.2.8  Clipper
      9. 2.2.9  Output Crossbar
      10. 2.2.10 DSP Memory Map
    3. 2.3  Process Flow 2
      1. 2.3.1 SRC
      2. 2.3.2 Input Mixer
      3. 2.3.3 Equalizer
      4. 2.3.4 Volume
      5. 2.3.5 2-Band DRC
      6. 2.3.6 AGL
      7. 2.3.7 Clipper
      8. 2.3.8 Output Crossbar
      9. 2.3.9 DSP Memory Map
    4. 2.4  Process Flow 3
      1. 2.4.1 SRC
      2. 2.4.2 Input Mixer
      3. 2.4.3 Equalizer
      4. 2.4.4 Volume
      5. 2.4.5 2-Band DRC
      6. 2.4.6 AGL
      7. 2.4.7 Clipper
      8. 2.4.8 Output Crossbar
      9. 2.4.9 DSP Memory Map
    5. 2.5  Process Flow 4
      1. 2.5.1 SRC
      2. 2.5.2 Volume
      3. 2.5.3 DSP Memory Map
    6. 2.6  Process Flow 5
      1. 2.6.1  SRC
      2. 2.6.2  Input Mixer
      3. 2.6.3  Equalizer
      4. 2.6.4  Volume
      5. 2.6.5  DPEQ
      6. 2.6.6  3-Band DRC
      7. 2.6.7  AGL
      8. 2.6.8  Clipper
      9. 2.6.9  Output Crossbar
      10. 2.6.10 DSP Memory Map
    7. 2.7  Process Flow 6
      1. 2.7.1 SRC
      2. 2.7.2 Input Mixer
      3. 2.7.3 Equalizer
      4. 2.7.4 Volume
      5. 2.7.5 2-Band DRC
      6. 2.7.6 AGL
      7. 2.7.7 Clipper
      8. 2.7.8 Output Crossbar
      9. 2.7.9 DSP Memory Map
    8. 2.8  Process Flow 7
      1. 2.8.1 SRC
      2. 2.8.2 Input Mixer
      3. 2.8.3 Equalizer
      4. 2.8.4 Volume
      5. 2.8.5 2-Band DRC
      6. 2.8.6 AGL
      7. 2.8.7 Clipper
      8. 2.8.8 Output Crossbar
      9. 2.8.9 DSP Memory Map
    9. 2.9  Process Flow 8
      1. 2.9.1 SRC
      2. 2.9.2 Volume
      3. 2.9.3 DSP Memory Map
    10. 2.10 Process Flow 9
      1. 2.10.1 SRC
      2. 2.10.2 Input Mixer
      3. 2.10.3 Equalizer
      4. 2.10.4 Volume
      5. 2.10.5 2-Band DRC
      6. 2.10.6 1-Band DRC
      7. 2.10.7 Output Crossbar
      8. 2.10.8 DSP Memory Map
  6. 3Audio Processing Blocks
    1. 3.1 Input Mixer
    2. 3.2 Equalizer
    3. 3.3 Volume
    4. 3.4 DPEQ
      1. 3.4.1 DPEQ
      2. 3.4.2 Energy Sense
      3. 3.4.3 Low Level EQ
      4. 3.4.4 High Level EQ
    5. 3.5 3-Band DRC
      1. 3.5.1 DRC Time Constant
      2. 3.5.2 Crossover
    6. 3.6 2-Band DRC
      1. 3.6.1 DRC Time Constant
      2. 3.6.2 Crossover
    7. 3.7 AGL
    8. 3.8 Clipper
    9. 3.9 Output Crossbar
  7.   A Appendix
    1.     A.1 DSP Memory Map for Process Flows 1 and 5
    2.     A.2 DSP Memory Map for Process Flow 2, 3, 6 and 7
    3.     A.3 DSP Memory Map for Process Flow 4 and 8
    4.     A.4 DSP Memory Map for Process 9

A.3 DSP Memory Map for Process Flow 4 and 8

Table 4-6 2.0 and 1.0 192kHz Mode Memory Map — Book 0x8C
SUB ADDRESS PAGE REGISTER NAME NUMBER OF BYTES/ FORMAT DEFAULT VALUE DESCRIPTION
BYPASS DCBLOCK
0x58 0x06 Bypass DC block 4 / 32.0 0x00000000 DC Block flag
INPUT MIXER
0x74 0x09 Left to Left 4 / 9.23 0x00800000

Left Channel Mixer Left

Input Gain
0x78 0x09 Right to Left 4 / 9.23 0x00000000

Left Channel Mixer Right

Input Gain
0x7C 0x09 Left to Right 4 / 9.23 0x00000000

Right Channel Mixer Left

Input Gain
0x08 0x0A Right to Right 4 / 9.23 0x00800000

Right Channel Mixer

Right Input Gain
CLASSH CONTROL
0x50 0x0A Bypass ClassH 4 / 32.0 0x00000000 ClassH Bypass flag
0x5C 0x0A Delay Left 4 / 32.0 0x000000F0 Left Channel Delay Samples
0x60 0x0A Delay Right 4 / 32.0 0x000000F0 Right Channel Delay Samples
0x68 0x0A Max Detect Window 4 / 32.0 0x00000000 Max Detect Window Samples
0x6C 0x0A Peak Hold 4 / 32.0 0x00000180 Peak Hold Samples
0x70 0x0A Peak Detect Offset 4 / 1.31 0x7FDF3B64 Peak Detect Offset linear
0x74 0x0A Peak Decay 4 / 1.31 0x7999999A Peak Decay linear
0x78 0x0A Peak Smooth 4 / 1.31 0x0538EF35 Peak Smooth Time constant
0x7C 0x0A State Threshold 4 / 5.27 0x00000000 ClassH State Threshold linear