SLVAE85A February   2019  – September 2025 LM1117-Q1 , LM317 , LP2951 , LP2951-Q1 , LP2985 , TL1963A , TL1963A-Q1 , TLV1117 , TLV709 , TLV755P , TLV761 , TLV766-Q1 , TLV767 , TLV767-Q1 , TPS709 , TPS709-Q1 , TPS715 , TPS745 , TPS7A16A , TPS7A16A-Q1 , TPS7A25 , TPS7A26 , TPS7A43 , TPS7A44 , TPS7A47 , TPS7A47-Q1 , TPS7A49 , TPS7B63-Q1 , TPS7B68-Q1 , TPS7B69-Q1 , TPS7B81 , TPS7B81-Q1 , TPS7B82-Q1 , TPS7B83-Q1 , TPS7B84-Q1 , TPS7B85-Q1 , TPS7B86-Q1 , TPS7B87-Q1 , TPS7B88-Q1 , TPS7B91 , TPS7B92 , TPS7C84-Q1 , UA78L , UA78M , UA78M-Q1

 

  1.   1
  2.   An empirical analysis of the impact of board layout on LDO thermal performance
  3.   Trademarks
  4. 1Introduction
  5. 2Procedure
  6. 3Test Results and Discussion
  7. 4Conclusion
  8. 5Future Study
  9. 6References
  10. 7Revision History
  11.   A Thermal Test Board Layouts
    1.     A.1 TPS745 (WSON) Drawings
      1.      A.1.1 1S0P Approximation Layout Drawings
      2.      A.1.2 Internally Disconnected Layout Drawings
      3.      A.1.3 JEDEC High-K Approximation Layout Drawings
      4.      A.1.4 Thermally Enhanced Layout Drawings
      5.      A.1.5 Thermally Saturated Layout Drawings
    2.     A.2 TPS7B82-Q1 (TO-252) Drawings
      1.      A.2.1 1S0P Approximation Layout Drawings
      2.      A.2.2 Internally Disconnected Layout Drawings
      3.      A.2.3 JEDEC High-K Approximation Layout Drawings
      4.      A.2.4 Thermally Enhanced Layout Drawings
      5.      A.2.5 Thermally Saturated Layout Drawings
    3.     A.3 TLV755P (SOT-23) Drawings
      1.      A.3.1 1S0P Approximation Layout Drawings
      2.      A.3.2 Internally Disconnected Layout Drawings
      3.      A.3.3 JEDEC High-K Approximation Layout Drawings
      4.      A.3.4 Thermally Enhanced Drawings
      5.      A.3.5 Thermally Saturated Layout Drawings
  12.   B Thermal Test Results
    1.     B.1 Thermal Performance Data

5 Future Study

There are a couple of areas that can be addressed in a future study. The first is to investigate these or similar layouts’ effect on ultra small (less than 1 mm2) packages like the DSBGA and X2SON that traditionally have poor thermal performance. Due to poor heat dissipative capability inherent to small packages, the PCB layout can have a reduced effect on the thermal performance compared to the WSON, TO-252, and SOT-23 packages. Another more complex extension of this study can develop an equation or Figure of Merit (FOM) that incorporates connected copper area, disconnected copper area, the location of these areas relative to the board stack up, number of thermal vias, and so forth. This FOM, which would correlate to an equivalent thermal impedance of the board, can be applied to provide a more targeted value for the expected θJA of a given layout.