1 Introduction

LDOs are the most common DC/DC converter in electronic power designs due to their relative simplicity and cost advantage. As applications become increasingly integrated and compact, power designs must become smaller and cheaper, resulting in more LDO content. As a result, thermal performance is an even more important system design factor as LDOs are linear converters and inherently power dissipative. While JEDEC has standardized the method to measure and report semiconductor thermal metrics in a uniform manner, the standard is not fully optimized for thermal performance. One of the most significant factors that affects thermal performance falls on the system designer, PCB layout. The goal of this application report is to aid these designers by investigating the effect of PCB layout on the thermal performance of LDOs. Although the LDOs thermal performance in small SMD packages application report and the AN-1520 a guide to board layout for best thermal resistance for exposed packages application report previously discussed this topic, this study aims to be more applicable by collecting data in a functional setting. This setting includes functional PCB layouts with passive components that emulate TI Evaluation Modules (EVMs), and thermal measurements taken through active powering. Active powering refers to placing the LDO in a normal operation and varying the input voltage and the load current to increase the power dissipation and generate heat at the junction of the device.

The most popular metric for evaluating semiconductor thermal performance is the junction-to-ambient thermal resistance, θ_JA. Equation 1 shows that this parameter is defined as the difference between the operating temperature and junction temperature of a device per watt of power dissipated in the device:

Equation 1.

A design with a smaller θ_JA has a lower junction temperature for a given level of power dissipation, improving longevity and reliability. Semiconductor and IC package thermal metrics application report explains that the two factors that have a large impact on θ_JA are the PCB layout and IC package. Three LDOs in common packages, the TPS745 (WSON package), TPS7B82-Q1 (TO-252 package), and TLV755P (SOT-23 package) are tested with five different PCB layouts and are chosen to investigate how much these two factors affect thermal performance.

The dependence of semiconductor thermal performance on additional external factors including air flow, altitude, and ambient temperature has resulted in the need for JEDEC to standardize measurement procedures and test boards for θ_JA and other thermal metrics. For this application report, approximations of the Low Effective Thermal Conductivity Test Board, described in https://www.jedec.org/system/files/docs/JESD51-3.PDF, and the High Effective Thermal Conductivity Test Board, described in https://www.jedec.org/system/files/docs/jesd51-7.PDF, are designed for each package along with three custom layouts. The area and layer stack of each board follow the JEDEC standard test board approximations: 4layer PCBs with an area of 9-in² (3-in by 3-in). The outer layers contain two ounce copper thickness while the inner layers contain one ounce copper thickness. The five layouts fabricated for each package contain increasing amounts of copper connected to the device with the intent to measure θ_JA and show an inverse relationship versus copper coverage. To improve the consistency of the results across the three packages, the amount of copper used for heat sinking in each type of layout is kept equal. In order of least to greatest copper content, the layout types are referred to as:

• 1S0P Approximation
• Internally Disconnected
• JEDEC High-K Approximation
• Thermally Enhanced
• Thermally Saturated

Thermal vias are also included in the thermal landing pad for all WSON and TO-252 layouts according to the JEDEC standard specified in https://www.jedec.org/system/files/docs/JESD51-9.pdf. These vias have a 20 millimeter (mm) diameter, 10-mm hole size, and 17-µm copper plating.

Two different θ_JA values are used as benchmarks for comparison. The first is θ_{JA, datasheet} as specified in the Thermal Information table in the datasheet of each device as R_θJA. θ_{JA, datasheet} is derived using a thermal model of the JEDEC High-K Thermal Test Board and is the most popular metric used by designers to evaluate thermal performance. The second value is θ_JA,1S0P, as measured with the 1S0P Approximation layout. This value provides an example of the expected thermal performance for a worst-case layout. Figure 1-1 through Figure 1-5 show 3D generated images for each of the layouts designed for the TPS745 in the WSON package. Drawings of all four layers for each layout can be found in Appendix A. Table 1-1 provides descriptions for each design layout and copper coverage.

Figure 1-1 TPS745 (WSON) 1S0P Approximation Layout

Figure 1-2 TPS745 (WSON) Internally Disconnected Layout

Figure 1-3 TPS745 (WSON) JEDEC High-K Approximation Layout

Figure 1-4 TPS745 (WSON) Thermally Enhanced Layout

Figure 1-5 TPS745 (WSON) Thermally Saturated Layout