SLVAFD0C May   2022  – August 2025 AM620-Q1 , AM623 , AM625 , AM625-Q1 , TPS65219 , TPS65219-Q1 , TPS65220

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
  5. 2 TPS65219 Overview
    1. 2.1 TPS65219 Functional Block Diagram
  6. 3 TPS65219 Variants
    1. 3.1 TPS65219 NVMs for Industrial Applications
    2. 3.2 TPS65219-Q1 NVMs for Automotive Applications
  7. 4 TPS6521905 User-Programmable NVM
  8. 5 AM62x Core Voltage Selection
  9. 6 VSYS Voltage Ramp
  10. 7 Power Block Diagrams
    1. 7.1 TPS6521901 Powering AM62x
    2. 7.2 TPS6521902 Powering AM62x
    3. 7.3 TPS6521903 Powering AM62x
    4. 7.4 TPS6521904 Powering AM62x
    5. 7.5 TPS6521907 Powering AM62x
    6. 7.6 TPS6521908 Powering AM62x
    7. 7.7 TPS6521920W-Q1 Powering AM62x-Q1
    8. 7.8 TPS6521922W-Q1 Powering AM62x-Q1
    9. 7.9 TPS6521923W-Q1 Powering AM62x-Q1
  11. 8 Summary
  12. 9 References
  13. 10Revision History

3.1 TPS65219 NVMs for Industrial Applications

Table 3-1 TPS65219 NVMs for AM62x Industrial Applications
TPS6521901 TPS6521902 TPS6521903 TPS6521904 TPS6521907 TPS6521908
Use Case Vsys 5V 3.3V 3.3V 3.3V 5V 3.3V
VDD_CORE(3) 0.75V 0.75V 0.75V 0.85V 0.85V 0.85V
External Memory DDR4 LPDDR4 DDR4 DDR4 DDR4 LPDDR4
Technical Reference Manual (TRM) SLVUCH3 SLVUCL0 SLVUCJ2 SLVUCL1 SLVUCL9 SLVUCM0
Hardware(2) TPS65219EVM AM62B starter kit with PMIC AM62B starter kit with PMIC
BUCK1 Vout 0.75V 0.75V 0.75V 0.85V 0.85V 0.85V
Bandwidth High bandwidth High bandwidth High bandwidth High bandwidth High bandwidth High bandwidth
BUCK2 Vout 3.3V 1.8V 1.8V 1.8V 3.3V 1.8V
Bandwidth High bandwidth High bandwidth High bandwidth High bandwidth High bandwidth High bandwidth
BUCK3 Vout 1.2V 1.1V 1.2V 1.2V 1.2V 1.1V
Bandwidth High bandwidth High bandwidth High bandwidth High bandwidth High bandwidth High bandwidth
LDO1 Vout 3.3V/1.8V (Bypass) 3.3V/1.8V (Bypass) 3.3V/1.8V (Bypass) 3.3V/1.8V (Bypass) 3.3V/1.8V (Bypass) 3.3V/1.8V (Bypass)
LDO2 Vout 0.85V 0.85V 0.85V 1.8V 1.8V 1.2V (Disabled)
LDO3 Vout 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V
LDO4 Vout 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V
GPIOs GPO1 Enabled Disabled Disabled Disabled Enabled Disabled
GPO2 Disabled Enabled Enabled Enabled Disabled Enabled
GPIO Disabled Disabled Disabled Disabled Disabled Disabled
MODE/RESET Config Warm Reset Warm Reset Warm Reset Warm Reset Warm Reset Warm Reset
Polarity High= Normal operation

Low=Warm Reset

 High= Normal operation

Low=Warm Reset

 High= Normal operation

Low=Warm Reset

 High= Normal operation

Low=Warm Reset

 High= Normal operation

Low=Warm Reset

 High= Normal operation

Low=Warm Reset
MODE/SBY Config Mode and Standby Mode and Standby Mode and Standby Mode and Standby Mode and Standby Mode and Standby
Polarity High=Active State and Forced-PWM

Low=Stby State and Auto-PFM

 High=Active State and Forced-PWM

Low=Stby State and Auto-PFM

 High=Active State and Forced-PWM

Low=Stby State and Auto-PFM

 High=Active State and Forced-PWM

Low=Stby State and Auto-PFM

 High=Active State and Forced-PWM

Low=Stby State and Auto-PFM

 High=Active State and Forced-PWM

Low=Stby State and Auto-PFM
VSEL_SD/DDR Config SD SD SD SD SD SD
Rail LDO1 LDO1 LDO1 LDO1 LDO1 LDO1
Polarity High = LDO1_VSET

Low = 1.8V

 High = LDO1_VSET

Low = 1.8V

 High = LDO1_VSET

Low = 1.8V

 High = LDO1_VSET

Low = 1.8V

 High = LDO1_VSET

Low = 1.8V

 High = LDO1_VSET

Low = 1.8V
EN/PB/VSENSE pin config Enable Push-button Push-button Push-button Enable Enable
First Supply detection (1) Enabled Enabled Enabled Enabled Enabled Enabled
(1) First Supply detection allows power-up as soon as supply voltage is applied, even if EN, PB, VSENSE pin is at OFF_REQ status. FSD can be used in combination with any ON-request configuration, EN, PB or VSENSE. At first power-up, the EN, PB, VSENSE pin is treated as if there was aValid ON request.
(2) The AM62 starter kit comes with the TPS6521904 PMIC by default, supporting VDD_CORE=0.85V. To supportVDD_CORE=0.75V, the following changes are required: TPS6521904 PMIC needs to be replaced with TPS6521903, R699 needs to be uninstalled, and R123 needs to be mounted.
(3) See Section 5 for a comparison of the two VDD_CORE operating points.