SLVAFD0C May   2022  – August 2025 AM620-Q1 , AM623 , AM625 , AM625-Q1 , TPS65219 , TPS65219-Q1 , TPS65220

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
  5. 2 TPS65219 Overview
    1. 2.1 TPS65219 Functional Block Diagram
  6. 3 TPS65219 Variants
    1. 3.1 TPS65219 NVMs for Industrial Applications
    2. 3.2 TPS65219-Q1 NVMs for Automotive Applications
  7. 4 TPS6521905 User-Programmable NVM
  8. 5 AM62x Core Voltage Selection
  9. 6 VSYS Voltage Ramp
  10. 7 Power Block Diagrams
    1. 7.1 TPS6521901 Powering AM62x
    2. 7.2 TPS6521902 Powering AM62x
    3. 7.3 TPS6521903 Powering AM62x
    4. 7.4 TPS6521904 Powering AM62x
    5. 7.5 TPS6521907 Powering AM62x
    6. 7.6 TPS6521908 Powering AM62x
    7. 7.7 TPS6521920W-Q1 Powering AM62x-Q1
    8. 7.8 TPS6521922W-Q1 Powering AM62x-Q1
    9. 7.9 TPS6521923W-Q1 Powering AM62x-Q1
  11. 8 Summary
  12. 9 References
  13. 10Revision History

7.9 TPS6521923W-Q1 Powering AM62x-Q1

VSYS = 3.3V or 5V | Memory: LPDDR4 | VDD_CORE = 0.75V | Automotive

Figure 7-9 shows the automotive TPS6521923W-Q1 variant powering the AM62x-Q1 processor on a system with 5V input supply and LDDR4 memory. Buck1, Buck2 and Buck3 are used to supply VDD_CORE at 0.75V, 3.3V VDDSHVy IO and 1.1V DDR IO, respectively. The GPO1 is preprogrammed to enable an external Buck to supply the 1.8V IO. LDO1 and LDO4 are disabled by default. LDO2 is used to supply the VDDR_CORE. LDO3 supports the 1.8V analog domain. GPIO and GPO1 are free digital resources that are disable by default but can be enabled through I2C if needed.

Note: Refer to the TPS6521923 Technical Reference Manual for a description of the NVM settings and power-up or power-down sequence diagrams.
TPS6521923W-Q1 Powering AM62x Figure 7-9 TPS6521923W-Q1 Powering AM62x