SLVAFD0C May   2022  – August 2025 AM620-Q1 , AM623 , AM625 , AM625-Q1 , TPS65219 , TPS65219-Q1 , TPS65220

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
  5. 2 TPS65219 Overview
    1. 2.1 TPS65219 Functional Block Diagram
  6. 3 TPS65219 Variants
    1. 3.1 TPS65219 NVMs for Industrial Applications
    2. 3.2 TPS65219-Q1 NVMs for Automotive Applications
  7. 4 TPS6521905 User-Programmable NVM
  8. 5 AM62x Core Voltage Selection
  9. 6 VSYS Voltage Ramp
  10. 7 Power Block Diagrams
    1. 7.1 TPS6521901 Powering AM62x
    2. 7.2 TPS6521902 Powering AM62x
    3. 7.3 TPS6521903 Powering AM62x
    4. 7.4 TPS6521904 Powering AM62x
    5. 7.5 TPS6521907 Powering AM62x
    6. 7.6 TPS6521908 Powering AM62x
    7. 7.7 TPS6521920W-Q1 Powering AM62x-Q1
    8. 7.8 TPS6521922W-Q1 Powering AM62x-Q1
    9. 7.9 TPS6521923W-Q1 Powering AM62x-Q1
  11. 8 Summary
  12. 9 References
  13. 10Revision History

3.2 TPS65219-Q1 NVMs for Automotive Applications

Table 3-2 TPS65219-Q1 NVMs for AM62x-Q1 Automotive Applications
TPS6521920W-Q1

TPS6521922W-Q1

TPS6521923W-Q1

Use CaseVsys3.3V

3.3V

5V
VDD_CORE(2)0.75V

0.85V

0.75V
External MemoryLPDDR4

LPDDR4

LPDDR4
Technical Reference Manual (TRM)SLVUCN8

SLVUDE1

SLVUCM6
HardwareAM62x starter kit for low-power Sitara processors
BUCK1Vout0.75V

0.85V

0.75V
BandwidthHigh bandwidthHigh bandwidthHigh bandwidth
BUCK2Vout1.8V

1.8V

3.3V
BandwidthHigh bandwidthHigh bandwidthLow Bandwidth
BUCK3Vout1.1V

1.1V

1.1V
BandwidthHigh bandwidthHigh bandwidthLow Bandwidth
LDO1Vout3.3V/1.8V (Bypass)3.3V/1.8V (Bypass)Disabled
LDO2Vout0.85V

0.85V

0.85V
LDO3Vout1.8V

1.8V

1.8V
LDO4Vout1.2V

1.2V

Disabled
GPIOsGPO1Disabled

Disabled

Enabled
GPO2Enabled

Enabled

Disabled
GPIODisabled

Disabled

Disabled
MODE/RESETConfigWarm Reset

Warm Reset

Warm Reset
PolarityHigh= Normal operation

Low=Warm Reset

High= Normal operation

Low=Warm Reset

High= Normal operation

Low=Warm Reset

MODE/SBYConfigMode

Mode

Standby
PolarityHigh=Forced-PWM

Low=Auto-PFM

High=Forced-PWM

Low=Auto-PFM

High=Standby State

Low=Active State

VSEL_SD/DDRConfigSD

SD

SD
RailLDO1

LDO1

LDO1
PolarityHigh = LDO1_VSET

Low = 1.8V

High = LDO1_VSET

Low = 1.8V

High = 1.8V

Low = LDO1_VSET

EN/PB/VSENSE pin configEnable

Enable

Enable
First Supply detection (1)Enabled

Enabled

Disabled
(1) First Supply detection allows power-up as soon as supplyVoltage is applied, even if EN, PB, VSENSE pin is at OFF_REQ status. FSD can be used in combination with any ON-request configuration, EN, PB orVSENSE. At first power-up the EN, PB, VSENSE pin is treated as if there was aValid ON request.
(2) See Section 5 for a comparison of the twoVDD_CORE operating points.