SLVAFD0C May   2022  – August 2025 AM620-Q1 , AM623 , AM625 , AM625-Q1 , TPS65219 , TPS65219-Q1 , TPS65220

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. Introduction
  5. TPS65219 Overview
    1. 2.1 TPS65219 Functional Block Diagram
  6. TPS65219 Variants
    1. 3.1 TPS65219 NVMs for Industrial Applications
    2. 3.2 TPS65219-Q1 NVMs for Automotive Applications
  7. TPS6521905 User-Programmable NVM
  8. AM62x Core Voltage Selection
  9. VSYS Voltage Ramp
  10. Power Block Diagrams
    1. 7.1 TPS6521901 Powering AM62x
    2. 7.2 TPS6521902 Powering AM62x
    3. 7.3 TPS6521903 Powering AM62x
    4. 7.4 TPS6521904 Powering AM62x
    5. 7.5 TPS6521907 Powering AM62x
    6. 7.6 TPS6521908 Powering AM62x
    7. 7.7 TPS6521920W-Q1 Powering AM62x-Q1
    8. 7.8 TPS6521922W-Q1 Powering AM62x-Q1
    9. 7.9 TPS6521923W-Q1 Powering AM62x-Q1
  11. Summary
  12. References
  13. 10Revision History

TPS6521920W-Q1 Powering AM62x-Q1

VSYS = 3.3V or 5V | Memory: LPDDR4 | VDD_CORE = 0.75V | Automotive

Figure 4-1 shows the automotive TPS6521920W-Q1 variant powering the AM62x-Q1 processor on a system with 3.3V input supply and LDDR4 memory. Buck1, Buck2 and Buck3 are used to supply VDD_CORE at 0.75V, 1.8V VDDSHVy IO and 1.1V DDR IO respectively. The 3.3V coming from the pre-regulator can be combined with a power switch to supply the 3.3 DVDDSHx IO domain. This external power switch is enabled or disabled by the PMIC and must have an active discharge. The GPO2 is preprogrammed to be enabled in the second slot of the power-up sequence with a duration of 10ms. This can be used to enable the external power switch and meet the processor sequence requirements. The switch must be selected with the right electrical spec to ramp and provide a stable output voltage within the 10ms duration of the second slot (before the PMIC start the next slot in the power-up sequence). LDO1, configured as bypass, allows dynamic SD card voltage changes between 3.3V and 1.8V. This voltage change on LDO1 can be triggered setting the VSEL_SD pin high (LDO1=3.3V) or low (LDO1=1.8 V). LDO2, is used to supply the VDDR_CORE. LDO3 supports the 1.8V analog domain. LDO4 is configured to output 1.2V and can be used to supply the HDMI transmitter. GPIO and GPO1 are free digital resources that are disable by default but can be enabled through I2C if needed.

The TPS6521920W-Q1 also supports 5V input supply. When using VSYS = 5V, replace the external power-switch with a 3.3V buck converter. This external buck converter is enabled by the same PMIC GPO2.

Note: Refer to the TPS6521920 Technical Reference Manual for a description of the NVM settings and power-up or power-down sequence diagrams.
 TPS6521920W-Q1 Powering
                    AM62x Figure 7-7 TPS6521920W-Q1 Powering AM62x