VSYS = 3.3V or 5V | Memory: LPDDR4 | VDD_CORE = 0.85V

Figure 7-6 shows the TPS6521908 variant powering the AM62x processor on a system with 3.3V input supply and LDDR4. In this configuration, Buck1 is configured with an output voltage of 0.85V to supply the CORE rails. As noted in the AM62x spec, VDD_CORE and VDDR_CORE are expected to be powered by the same source so these ramp together when VDD_CORE is operating at 0.85V. This requirement on the processor allows to have both, VDD_CORE and VDDR_CORE supplied by the same PMIC rail (Buck1). Buck2 and Buck3 supply the 1.8V IO domain and the LPDDR voltage, respectively. LDO1, configured as bypass, allows dynamic SD card voltage changes between 3.3V and 1.8V. This voltage change on LDO1 can be triggered by I2C or by setting the VSEL_SD pin high (LDO1=3.3V) or low (LDO1=1.8V). LDO3 supplies the 1.8V analog domain. LDO2 and LDO4 are free power resource that can be used to supply external peripherals. This NVM variant also has GPO2 preprogrammed to be enabled in the second slot of the power-up sequence with a duration of 10ms. This can be used to enable the external power switch and meet the processor sequence requirements. The power switch must be selected with the right electrical spec to ramp and provide a stable output voltage within the 10ms duration of the second slot (before the PMIC start the next slot in the power-up sequence).

The TPS6521908 also supports 5V input supply. When using VSYS = 5V, replace the external power-switch with a 3.3V buck converter. This external buck converter is enabled by the same PMIC GPO2.

Figure 7-6 TPS6521908 Powering AM62