VSYS = 5V | Memory: DDR4 | VDD_CORE = 0.85V

Figure 7-5 shows the TPS6521907 variant powering the AM62x processor on a system with 5V input supply and DDR4 memory. This PMIC NVM is similar to the TPS6521901 but supports VDD_CORE=0.85V instead of 0.75V. The 5V coming from the pre-regulator is connected to the main input supply for reference system (VSYS) and to the power input of the buck converters (PVIN_Bx). Buck1 is used to supply the CORE rails at 0.85V. Buck2 and Buck3 supply the 3.3V VDDSHVx IO and DDR IO respectively. Buck2 (3.3V PMIC rail) is programmed to ramp up first in the power-up sequence and can be used as the input supply for some of the LDOs to minimize power dissipation. LDO1, configured as bypass, allows dynamic SD card voltage changes between 3.3V and 1.8V. This voltage change on LDO1 can be triggered by I2C or by setting the VSEL_SD pin high (LDO1=3.3V) or low (LDO1=1.8V). LDO2, is a free resource that can be used to supply external peripherals. LDO3 supports the 1.8V analog domain and LDO4 supports the 2.5V VPP for the DDR4 memory. This power implementation requires an external discrete buck regulator to supply the 1.8V VDDSHV IO domain. This external discrete can be enabled using the GPO1 of the PMIC. TPS6521907 comes preprogrammed to enable GPO1 in the second slot of the power-up sequence. The external discrete has active discharge and must ramp up and reach a stable output voltage before the PMIC starts powering up the rails in the next slot. The remaining two general purpose pins (GPIO and GPO2) are free digital resources that are disabled by default but can be enabled through I2C after the PMIC completes the power-up sequence.

Figure 7-5 TPS6521907 Powering AM62