SLVSIM8A June   2025  – December 2025 DRV8363-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Functions 48-Pin DRV8363-Q1
  6. 5 Specification
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Recommended Operating Conditions
    3. 5.3 Thermal Information 1pkg
    4. 5.4 Electrical Characteristics
    5. 5.5 SPI Timing Requirements
    6. 5.6 SPI Timing Diagrams
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Three BLDC Gate Drivers
        1. 6.3.1.1 PWM Control Modes
          1. 6.3.1.1.1 6x PWM Mode
          2. 6.3.1.1.2 3x PWM Mode with INLx enable control
          3. 6.3.1.1.3 1x PWM Mode
        2. 6.3.1.2 Gate Drive Architecture
          1. 6.3.1.2.1 Bootstrap diode
          2. 6.3.1.2.2 VCP Trickle Charge pump
          3. 6.3.1.2.3 Gate Driver Output
          4. 6.3.1.2.4 Passive and Semi-active pull-down resistor
          5. 6.3.1.2.5 TDRIVE/IDRIVE Gate Drive Timing Control
          6. 6.3.1.2.6 Propagation Delay
          7. 6.3.1.2.7 Deadtime and Cross-Conduction Prevention
      2. 6.3.2 DVDD Linear Voltage Regulator
      3. 6.3.3 Low-Side Current Sense Amplifiers
        1. 6.3.3.1 Unidirectional Current Sense Operation
        2. 6.3.3.2 Bidirectional Current Sense Operation
      4. 6.3.4 Gate Driver Shutdown
        1. 6.3.4.1 DRVOFF Gate Driver Shutdown
        2. 6.3.4.2 Soft Shutdown Timing Sequence
      5. 6.3.5 Active Short Circuit
      6. 6.3.6 Gate Driver Protective Circuits
        1. 6.3.6.1  GVDD Undervoltage Lockout (GVDD_UV)
        2. 6.3.6.2  GVDD Overvoltage Fault (GVDD_OV)
        3. 6.3.6.3  VDRAIN Undervoltage Fault (VDRAIN_UV)
        4. 6.3.6.4  VDRAIN Overvoltage Fault (VDRAIN_OV)
        5. 6.3.6.5  VCP Undervoltage Fault (CP_OV)
        6. 6.3.6.6  BST Undervoltage Lockout (BST_UV)
        7. 6.3.6.7  MOSFET VDS Overcurrent Protection (VDS_OCP)
        8. 6.3.6.8  MOSFET VGS Monitoring Protection
        9. 6.3.6.9  Shunt Overcurrent Protection (SNS_OCP)
        10. 6.3.6.10 Thermal Shutdown (OTSD)
        11. 6.3.6.11 Thermal Warning (OTW)
        12. 6.3.6.12 OTP CRC
        13. 6.3.6.13 SPI Watchdog Timer
        14. 6.3.6.14 Phase Diagnostic
    4. 6.4 Fault Detection and Response Summary Table (Fault Table)
    5. 6.5 Device Functional Modes
      1. 6.5.1 Gate Driver Functional Modes
        1. 6.5.1.1 Sleep Mode
        2. 6.5.1.2 Standby Mode
        3. 6.5.1.3 Active Mode
    6. 6.6 Programming
      1. 6.6.1 SPI
      2. 6.6.2 SPI Format
      3. 6.6.3 SPI Format Diagrams
    7. 6.7 Register Maps
      1. 6.7.1 STATUS Registers
      2. 6.7.2 CONTROL Registers
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Typical Application with 48-pin package
        1. 7.2.1.1 External Components
      2. 7.2.2 Application Curves
    3. 7.3 Layout
      1. 7.3.1 Layout Guidelines
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1.     PACKAGE OPTION ADDENDUM
    2. 10.1 Tape and Reel Information
6.3.1.1.3 1x PWM Mode

In 1x PWM mode, the device uses 6-step block commutation tables that are stored internally. This feature allows for a three-phase BLDC motor to be controlled using one PWM sourced from a simple controller. The PWM is applied on the INHA pin and determines the output frequency and duty cycle of the half-bridges.

The half-bridge output states are managed by the INLA, INHB, and INLB pins which are used as state logic inputs. The state inputs can be controlled by an external controller or connected directly to the digital outputs of the Hall effect sensor from the motor (INLA = HALL_A, INHB = HALL_B, INLB = HALL_C). The 1x PWM mode usually operates with synchronous rectification (low-side MOSFET recirculation).

The INHC input controls the direction through the 6-step commutation table which is used to change the direction of the motor when Hall effect sensors are directly controlling the state of the INLA, INHB, and INLB inputs. Tie the INHC pin low if this feature is not required.

The INLC input brakes the motor by turning off all high-side MOSFETs and turning on all low-side MOSFETs when the INLC pin is pulled low. This brake is independent of the state of the other input pins. Tie the INLC pin high if this feature is not required.

Table 6-3 Synchronous 1x PWM Mode (PWM1X_COM = 0b)
LOGIC AND HALL INPUTSGATE DRIVE OUTPUTS(1)
STATEINHC = 0INHC = 1PHASE APHASE BPHASE CDESCRIPTION
INLAINHBINLBINLAINHBINLBGHAGLAGHBGLBGHCGLC
Stop000000LLLLLLStop
Align111111PWM!PWMLHLHAlign
1110001LLPWM!PWMLHB → C
2100011PWM!PWMLLLHA → C
3101010PWM!PWMLHLLA → B
4001110LLLHPWM!PWMC → B
5011100LHLLPWM!PWMC → A
6010101LHPWM!PWMLLB → A
(1) !PWM is the inverse of the PWM signal.
Table 6-4 Asynchronous 1x PWM Mode (PWM1X_COM = 1b)
LOGIC AND HALL INPUTSGATE DRIVE OUTPUTS
STATEINHC = 0INHC = 1PHASE APHASE BPHASE CDESCRIPTION
INLAINHBINLBINLAINHBINLBGHAGLAGHBGLBGHCGLC
Stop000000LLLLLLStop
Align111111PWMLLHLHAlign
1110001LLPWMLLHB → C
2100011PWMLLLLHA → C
3101010PWMLLHLLA → B
4001110LLLHPWMLC → B
5011100LHLLPWMLC → A
6010101LHPWMLLLB → A

Figure 6-2 and Figure 6-3 show the different possible configurations in 1x PWM mode.

DRV8363-Q1 1x PWM—Simple ControllerFigure 6-2 1x PWM—Simple Controller
DRV8363-Q1 1x PWM—Hall Effect SensorFigure 6-3 1x PWM—Hall Effect Sensor