SLVSIM8 Data sheet

SLVSIM8A June 2025 – December 2025 DRV8363-Q1

PRODUCTION DATA

6.7.2 CONTROL Registers

Table 6-18 lists the memory-mapped registers for the CONTROL registers. All register offset addresses not listed in Table 6-18 should be considered as reserved locations and the register contents should not be modified.

Table 6-18 CONTROL Registers

Offset	Acronym	Description	Section
9h	IC_CTRL1	IC Control Register 1	Section 6.7.2.1
Ah	IC_CTRL2	IC Control Register 2	Section 6.7.2.2
Bh	GD_CTRL1	Gate Drive Control Register 1	Section 6.7.2.3
Ch	GD_CTRL2	Gate Drive Control Register 2	Section 6.7.2.4
Dh	GD_CTRL3	Gate Drive Control Register 3	Section 6.7.2.5
Eh	GD_CTRL4	Gate Drive Control Register 4	Section 6.7.2.6
Fh	GD_CTRL5	Gate Drive Control Register 5	Section 6.7.2.7
13h	CSA_CTRL1	CSA Control Register 1	Section 6.7.2.8
14h	CSA_CTRL2	CSA Control Register 2	Section 6.7.2.9
15h	MON_CTRL1	Monitor Control Register 1	Section 6.7.2.10
16h	MON_CTRL2	Monitor Control Register 2	Section 6.7.2.11
17h	MON_CTRL3	Monitor Control Register 3	Section 6.7.2.12
18h	MON_CTRL4	Monitor Control Register 4	Section 6.7.2.13
19h	MON_CTRL5	Monitor Control Register 5	Section 6.7.2.14
1Ah	MON_CTRL6	Monitor Control Register 6	Section 6.7.2.15
1Bh	DIAG_CTRL1	Diagnostic Control Register 1	Section 6.7.2.16
1Ch	IC_CTRL_SP	IC Control Special Register	Section 6.7.2.17

Complex bit access types are encoded to fit into small table cells. Table 6-19 shows the codes that are used for access types in this section.

Table 6-19 CONTROL Access Type Codes

Access Type	Code	Description
Read Type
R	R	Read
Write Type
W	W	Write
Reset or Default Value
-n		Value after reset or the default value

6.7.2.1 IC_CTRL1 Register (Offset = 9h) [Reset = 0106h]

IC_CTRL1 is shown in Table 6-20.

Return to the Summary Table.

Table 6-20 IC_CTRL1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	DIS_PWM_INPUT	R/W	0h	Disable PWM inputs 0h = Gate driver outputs are controlled by INHx and INL digital inputs. 1h = INHx and INLx digital inputs are ignored and the gate driver outputs are pulled low (active pull down) by default.
14	WARN_MODE	R/W	0h	Warning nFAULT mode; Control nFAULT response for warning events 0h = No nFAULT reporting for warning response. Status flags are set. 1h = nFAULT is driven low for warning response. Status flags are set.
13	DIS_SSC	R/W	0h	TI Internal design parameter: No change is required unless notified by TI. The bit disables Spread Spectrum Clocking feature of the device internal oscillator 0h = Normal operation. Spread Spectrum Clocking feature is enabled. 1h = Spread Spectrum Clock feature is disabled for TI debug purpose.
12	RESERVED	R	0h	Reserved
11	ASC_LS_FORCE	R/W	0h	Force LS ASC under any non-global-shutdown condition (even under OCP_VDS_LS_x fault) if LS ASC is activated. This will not affect HS ASC. 0h = LS ASC is not forced 1h = LS ASC is forced as described
10	ASC_POLARITY	R/W	0h	ASC on LS or HS 0h = ASC by turning ON all LS FETs 1h = ASC by turning ON all HS FETs
9	SPI_ASC_EN	R/W	0h	Enable ASC (OR'ed with ASCIN pin) 0h = Normal operation mode 1h = Enable ASC
8	ASC_PRIORITY	R/W	1h	ASC priority over faults other than OTSD, GVDD_UVH, GVDDD_OV, and DRVOFF. These three listed faults have always priority over ASC. 0h = ASC has lower priority than all faults 1h = ASC has priority over faults other than OTSD, GVDD_UVH and DRVOFF (default)
7	RESERVED	R	0h	Reserved
6	RESERVED	R	0h	Reserved
5	RESERVED	R	0h	Reserved
4	RESERVED	R	0h	Reserved
3-1	LOCK	R/W	3h	Lock and unlock the register setting Bit settings not listed have no effect. 3h = Unlock all the registers 6h = Lock the settings by ignoring further register writes except to these bits.
0	CLR_FLT	R/W	0h	Clear fault. After fault event is detected and fault flag is set, it's recommended to issue CLR_FLT command first, then ENABLE_DRV command next in a separate SPI frame. If CLR_FLT and ENABLE_DRV commmands are issued in the same SPI frame, CLR_FLT is higher priority and ENABLE_DRV will not be set if fault flag is already latched and the device is waiting CLR_FLT. 0h = No action 1h = Clear faults. Bit will not self-clear, but clear fault operation is only performed once when this register/bit is written.

6.7.2.2 IC_CTRL2 Register (Offset = Ah) [Reset = 0000h]

IC_CTRL2 is shown in Table 6-21.

Return to the Summary Table.

Table 6-21 IC_CTRL2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RESERVED	R	0h	Reserved
14	RESERVED	R	0h	Reserved
13	RESERVED	R	0h	Reserved
12	RESERVED	R	0h	Reserved
11	RESERVED	R	0h	Reserved
10	RESERVED	R	0h	Reserved
9	RESERVED	R	0h	Reserved
8	RESERVED	R	0h	Reserved
7	RESERVED	R	0h	Reserved
6	TCP_SW_CURLIM	R/W	0h	TCP Switch current limit after TCP_SW_DLY 0h = 1.25mA (typ) 1h = 2.3mA (typ)
5-4	TCP_SW_HD_CURLIM	R/W	0h	TCP Switch HD current limit for High Duty cycle (TCP_HD_DIS=0) 0h = 7.7mA (typ) 1h = 6.4mA (typ) 2h = 10.5mA (typ) 3h = 9.2mA (typ)
3	TCP_SW_DLY	R/W	0h	Delay time to activate trickle charge pump after the device detects PWM inactive (INHx=INLx=Low) 0h = 100us (typ) 1h = 250us (typ)
2	TCP_HD_DIS	R/W	0h	VCP/TCP high-duty disabled 0h = TCP High-Duty cycle is enabled 1h = TCP High-Duty cycle is disabled
1-0	TCP_SW_MODE	R/W	0h	VCP/TCP mode control 0h = Normal VCP/TCP operation. VCP/TCP is enabled at power up. TCP SW responds to PWM inputs. TCP SW is enabled even if SPI DIS_PWM_INPUT is 1. When DRVOFF is high and if system expects the device to keep BST cap stay charged, TCP_SW_MODE must be 00b. 1h = VCP/CPTH-SHx switch is disabled. VCP/TCP charge pump clock is active. 2h = VCP/TCP shutdown. Both VCP/CPTH-SHx switch and VCP/TCP charge pump clock are disabled. 3h = Normal VCP/TCP operation. VCP/TCP is enabled at power up.

6.7.2.3 GD_CTRL1 Register (Offset = Bh) [Reset = 0038h]

GD_CTRL1 is shown in Table 6-22.

Return to the Summary Table.

Table 6-22 GD_CTRL1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	PWM1X_COM	R/W	0h	1x PWM Commutation Control 0h = 1x PWM mode uses synchronous rectification 1h = 1x PWM mode uses asynchronous rectification
14	PWM1X_DIR	R/W	0h	1x PWM Direction. In 1x PWM mode this bit is ORed with the INHC (DIR) input
13-12	PWM1X_BRAKE	R/W	0h	1x PWM output configuration 0h = Outputs follow commanded inputs 1h = Turn on all three low-side MOSFETs 2h = Turn on all three high-side MOSFETs 3h = Turn off all six MOSFETs (coast)
11	RESERVED	R	0h	Reserved
10	RESERVED	R	0h	Reserved
9-8	PWM_MODE	R/W	0h	PWM mode 0h = 6x PWM mode (INHx/INLx) 1h = 3x PWM mode with INLx enable control 2h = 1x PWM mode (INHx/INLx) 3h = Independent
7	STP_MODE_6X	R/W	0h	Control reporting for STP faults in 6xPWM mode 0h = Reporting enabled (outputs forced low) 1h = Reporting disabled (outputs forced low)
6-3	DEADT	R/W	7h	Gate driver dead time 0h = 70ns 1h = 120ns 2h = 180ns 3h = 300ns 4h = 400ns 5h = 500ns 6h = 600ns 7h = 750ns 8h = 1000ns 9h = 1.5us Ah = 2us Bh = 2.5us Ch = 3us Dh = 3.5us Eh = 5us Fh = 10us
2	DEADT_MODE	R/W	0h	Open Loop/Closed Loop 0h = Dead time is inserted when device input (INHx or INLx) goes low 1h = Dead time is inserted by monitoring gate driver outputs (GHx or GLx)
1-0	DEADT_MODE_6X	R/W	0h	Dead Time Violation Response Mode for 6 PWM mode only. NOTE: Other than 6 PWM mode, dead time is always inserted regardless of the DEADT_MODE bit and no fault is reported to the MCU. 0h = Dead-time protection is enabled. Reporting is performed. Gate driver control signals are enforced low during the dead time period. SPI fault flag is set and nFAULT pin is driven low when dead time condition is detected. 1h = Dead-time protection is enabled. Reporting is not performed. Gate driver control signals are enforced low during the dead time period. SPI fault flag is never set and nFAULT pin stays high when dead time condition is detected. 2h = Dead-time protection is disabled. No dead time is inserted. No SPI fault flag is set and the nFAULT1 pin stays high. This is applied to both cases when DEADT_MODE is 0b (monitoring INH or INL) and 1b (monitoring GHx or GLx). 3h = Dead-time protection is enabled and SPI fault is set but no nFAULT reporting is performed. Gate driver outputs are forced low during dead time period. nFAULT pin stays high when dead time condition is detected.

6.7.2.4 GD_CTRL2 Register (Offset = Ch) [Reset = 7700h]

GD_CTRL2 is shown in Table 6-23.

Return to the Summary Table.

Table 6-23 GD_CTRL2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-12	TDRVP	R/W	7h	Peak source pull up drive timing 0h = 200ns 1h = 300ns 2h = 400ns 3h = 500ns 4h = 650ns 5h = 750ns 6h = 900ns 7h = 1000ns 8h = 1.4us 9h = 1.6us Ah = 2us Bh = 2.2us Ch = 2.6us Dh = 3us Eh = 3.5us Fh = 4us
11-8	TDRVN	R/W	7h	Peak sink pull down drive timing 0h = 200ns 1h = 300ns 2h = 400ns 3h = 500ns 4h = 650ns 5h = 750ns 6h = 900ns 7h = 1000ns 8h = 1.4us 9h = 1.6us Ah = 2us Bh = 2.2us Ch = 2.6us Dh = 3us Eh = 3.5us Fh = 4us
7	RESERVED	R	0h	Reserved
6	RESERVED	R	0h	Reserved
5	RESERVED	R	0h	Reserved
4	IHOLD_SEL	R/W	0h	Select IHOLD pull-up and pull-down current. IHOLD_SEL bit must be configured while PWM is inactive (ENABLE_DRV is 0b). 0h = IHOLD pull-up 1024mA (typ) 1h = IHOLD pull-up 256mA (typ)
3-0	IDRVN_SD	R/W	0h	Soft shutdown drive current. 0h = 32mA 1h = 64mA 2h = 128mA 3h = 192mA 4h = 256mA 5h = 320mA 6h = 384mA 7h = 448mA 8h = 512mA 9h = 576mA Ah = 640mA Bh = 768mA Ch = 1024mA Dh = 1536mA Eh = 2048mA Fh = 2048mA

6.7.2.5 GD_CTRL3 Register (Offset = Dh) [Reset = 0000h]

GD_CTRL3 is shown in Table 6-24.

Return to the Summary Table.

Table 6-24 GD_CTRL3 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-12	IDRVP_HA	R/W	0h	High-side A peak source pull up current. 0h = 16mA 1h = 32mA 2h = 64mA 3h = 96mA 4h = 128mA 5h = 160mA 6h = 192mA 7h = 224mA 8h = 256mA 9h = 288mA Ah = 320mA Bh = 384mA Ch = 512mA Dh = 768mA Eh = 1024mA Fh = 1024mA
11-8	IDRVN_HA	R/W	0h	High-side A peak sink pull down current. 0h = 32mA 1h = 64mA 2h = 128mA 3h = 192mA 4h = 256mA 5h = 320mA 6h = 384mA 7h = 448mA 8h = 512mA 9h = 576mA Ah = 640mA Bh = 768mA Ch = 1024mA Dh = 1536mA Eh = 2048mA Fh = 2048mA
7-4	IDRVP_LA	R/W	0h	Low-side A peak source pull up current. 0h = 16mA 1h = 32mA 2h = 64mA 3h = 96mA 4h = 128mA 5h = 160mA 6h = 192mA 7h = 224mA 8h = 256mA 9h = 288mA Ah = 320mA Bh = 384mA Ch = 512mA Dh = 768mA Eh = 1024mA Fh = 1024mA
3-0	IDRVN_LA	R/W	0h	Low-side A peak sink pull down current. 0h = 32mA 1h = 64mA 2h = 128mA 3h = 192mA 4h = 256mA 5h = 320mA 6h = 384mA 7h = 448mA 8h = 512mA 9h = 576mA Ah = 640mA Bh = 768mA Ch = 1024mA Dh = 1536mA Eh = 2048mA Fh = 2048mA

6.7.2.6 GD_CTRL4 Register (Offset = Eh) [Reset = 0000h]

GD_CTRL4 is shown in Table 6-25.

Return to the Summary Table.

Table 6-25 GD_CTRL4 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-12	IDRVP_HB	R/W	0h	High-side B peak source pull up current. 0h = 16mA 1h = 32mA 2h = 64mA 3h = 96mA 4h = 128mA 5h = 160mA 6h = 192mA 7h = 224mA 8h = 256mA 9h = 288mA Ah = 320mA Bh = 384mA Ch = 512mA Dh = 768mA Eh = 1024mA Fh = 1024mA
11-8	IDRVN_HB	R/W	0h	High-side B peak sink pull down current. 0h = 32mA 1h = 64mA 2h = 128mA 3h = 192mA 4h = 256mA 5h = 320mA 6h = 384mA 7h = 448mA 8h = 512mA 9h = 576mA Ah = 640mA Bh = 768mA Ch = 1024mA Dh = 1536mA Eh = 2048mA Fh = 2048mA
7-4	IDRVP_LB	R/W	0h	Low-side B peak source pull up current. 0h = 16mA 1h = 32mA 2h = 64mA 3h = 96mA 4h = 128mA 5h = 160mA 6h = 192mA 7h = 224mA 8h = 256mA 9h = 288mA Ah = 320mA Bh = 384mA Ch = 512mA Dh = 768mA Eh = 1024mA Fh = 1024mA
3-0	IDRVN_LB	R/W	0h	Low-side B peak sink pull down current. 0h = 32mA 1h = 64mA 2h = 128mA 3h = 192mA 4h = 256mA 5h = 320mA 6h = 384mA 7h = 448mA 8h = 512mA 9h = 576mA Ah = 640mA Bh = 768mA Ch = 1024mA Dh = 1536mA Eh = 2048mA Fh = 2048mA

6.7.2.7 GD_CTRL5 Register (Offset = Fh) [Reset = 0000h]

GD_CTRL5 is shown in Table 6-26.

Return to the Summary Table.

Table 6-26 GD_CTRL5 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-12	IDRVP_HC	R/W	0h	High-side C peak source pull up current. 0h = 16mA 1h = 32mA 2h = 64mA 3h = 96mA 4h = 128mA 5h = 160mA 6h = 192mA 7h = 224mA 8h = 256mA 9h = 288mA Ah = 320mA Bh = 384mA Ch = 512mA Dh = 768mA Eh = 1024mA Fh = 1024mA
11-8	IDRVN_HC	R/W	0h	High-side C peak sink pull down current. 0h = 32mA 1h = 64mA 2h = 128mA 3h = 192mA 4h = 256mA 5h = 320mA 6h = 384mA 7h = 448mA 8h = 512mA 9h = 576mA Ah = 640mA Bh = 768mA Ch = 1024mA Dh = 1536mA Eh = 2048mA Fh = 2048mA
7-4	IDRVP_LC	R/W	0h	Low-side C peak source pull up current. 0h = 16mA 1h = 32mA 2h = 64mA 3h = 96mA 4h = 128mA 5h = 160mA 6h = 192mA 7h = 224mA 8h = 256mA 9h = 288mA Ah = 320mA Bh = 384mA Ch = 512mA Dh = 768mA Eh = 1024mA Fh = 1024mA
3-0	IDRVN_LC	R/W	0h	Low-side C peak sink pull down current. 0h = 32mA 1h = 64mA 2h = 128mA 3h = 192mA 4h = 256mA 5h = 320mA 6h = 384mA 7h = 448mA 8h = 512mA 9h = 576mA Ah = 640mA Bh = 768mA Ch = 1024mA Dh = 1536mA Eh = 2048mA Fh = 2048mA

6.7.2.8 CSA_CTRL1 Register (Offset = 13h) [Reset = 0000h]

CSA_CTRL1 is shown in Table 6-27.

Return to the Summary Table.

Table 6-27 CSA_CTRL1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RESERVED	R	0h	Reserved
14	RESERVED	R	0h	Reserved
13	RESERVED	R	0h	Reserved
12	RESERVED	R	0h	Reserved
11	RESERVED	R	0h	Reserved
10	RESERVED	R	0h	Reserved
9	RESERVED	R	0h	Reserved
8	RESERVED	R	0h	Reserved
7	RESERVED	R	0h	Reserved
6	RESERVED	R	0h	Reserved
5-4	CSA_AZ_TMAX	R/W	0h	Max delay to toggle CSA_CLK if no PWM input switching 0h = 250us 1h = 1ms 2h = 5ms 3h = No delay
3	CSA_AZ_DIS	R/W	0h	Current Sense Amplifier Auto Zero function disable 0h = CSA Auto Zero function is enabled. This bit should be 0b during normal PWM/CSA operation. 1h = CSA Auto Zero function is disabled. The purpose of this bit is to disable switching activity of current sense amplifier for auto zero function. Refer to timing requirements if this bit is used.
2	CSA_A_DIS	R/W	0h	Disable CSA channel A 0h = CSA channel A enabled 1h = CSA channel A disabled
1	CSA_B_DIS	R/W	0h	Disable CSA channel A 0h = CSA channel B enabled 1h = CSA channel B disabled
0	CSA_C_DIS	R/W	0h	Disable CSA channel C 0h = CSA channel C enabled 1h = CSA channel C disabled

6.7.2.9 CSA_CTRL2 Register (Offset = 14h) [Reset = 0000h]

CSA_CTRL2 is shown in Table 6-28.

Return to the Summary Table.

Table 6-28 CSA_CTRL2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	AREF_DIV	R/W	0h	VREF dividing ratio 0h = 1/2 1h = 1/8
14	RESERVED	R	0h	Reserved
13	RESERVED	R	0h	Reserved
12	RESERVED	R	0h	Reserved
11-8	WDT_TEST	R/W	0h	SPI Test field, write access here has no effect on device settings. Also used for WDT, any valid SPI write to this field will reset the watchdog timer if accessed within the correct window.
7	RESERVED	R	0h	Reserved
6	RESERVED	R	0h	Reserved
5-4	CSA_GAIN_A	R/W	0h	CSA Gain of SOA. Gain can be updated during PWM operation. Undefined settings (1001b - 1111b) are 40. 0h = 5 1h = 10 2h = 20 3h = 40
3-2	CSA_GAIN_B	R/W	0h	CSA Gain of SOB. Gain can be updated during PWM operation. Undefined settings (1001b - 1111b) are 40. 0h = 5 1h = 10 2h = 20 3h = 40
1-0	CSA_GAIN_C	R/W	0h	CSA Gain of SOC. Gain can be updated during PWM operation. Undefined settings (1001b - 1111b) are 40. 0h = 5 1h = 10 2h = 20 3h = 40

6.7.2.10 MON_CTRL1 Register (Offset = 15h) [Reset = 4000h]

MON_CTRL1 is shown in Table 6-29.

Return to the Summary Table.

Table 6-29 MON_CTRL1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-14	VDRAIN_OV_LVL	R/W	1h	VDRAIN Overvoltage threshold level 0h = 36V (typ) 1h = 54V (typ) 2h = 72V (typ) 3h = 84V (typ)
13-12	VDRAIN_UVH_LVL	R/W	0h	VDRAIN UV High threshold level 0h = 18V 1h = 20V 2h = 22V 3h = 24V
11	VDRAIN_UVL_LVL	R/W	0h	VDRAIN UV Low threshold level 0h = 10.5V 1h = 5.55V
10-8	VDRAIN_OV_MODE	R/W	0h	When set for ASC mode: HS or LS ASC from ASC_POLARITY bit If VDRAIN_OV=1 while WPD on VDS response then ASC and LS APD (no WPD) regardless of ASC_POLARITY 0h = Warning mode (latched) 1h = Fault mode (latched) 2h = ASC mode (latched, HS or LS based on ASC_POLARITY or VDS fault) 3h = ASC mode (autorecovery, HS or LS based on ASC_POLARITY or VDS fault) 4h = Default mode 5h = Default mode 6h = Default mode 7h = No report. No shutdown.
7-6	VDRAIN_UVH_MODE	R/W	0h	VDRAIN monitor mode for under voltage monitor 0h = Warning mode (latched) 1h = Fault mode (latched) 2h = Warning mode (autorecovery) 3h = No report. No shutdown.
5-4	VDRAIN_UVL_MODE	R/W	0h	VDRAIN monitor mode for under voltage monitor 0h = Warning mode (latched) 1h = Fault mode (latched) 2h = Warning mode (autorecovery) VDS faults are disabled 3h = No report. No shutdown.
3	GVDD_UVH_MODE	R/W	0h	GVDD_UVH monitor mode 0h = Warning mode (latched) 1h = Fault mode (latched)
2-1	GVDD_UV_BST_MODE	R/W	0h	GVDD_UV_BST monitor mode. nFAULT remains high regardless of WARN_MODE. 0h = Warning mode (autorecovery), VCP_UV input remains enabled, BST_UV_LVL not forced 1h = Warning special mode (latched), VCP_UV input disabled, BST_UV_LVL is 1 2h = Warning special mode (autorecovery), VCP_UV input disabled, BST_UV_LVL is 1 3h = No report. No action.
0	GVDD_UV_BST_LVL	R/W	0h	GVDD_UV_BST monitor threshold level. 0h = 10.6V (typ) 1h = 9.6V (typ)

6.7.2.11 MON_CTRL2 Register (Offset = 16h) [Reset = 8003h]

MON_CTRL2 is shown in Table 6-30.

Return to the Summary Table.

Table 6-30 MON_CTRL2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	GVDD_OV_MODE	R/W	1h	GVDD monitor mode of over voltage monitor 0h = Warning mode (latched) 1h = Fault mode (latched)
14	VDRAIN_UVL_MASK	R/W	0h	If active it masks VDRAIN_UVL during first power-up sequence. 0h = Normal operation 1h = VDRAIN_UVL is masked during first power-up sequence
13	RESERVED	R	0h	Reserved
12	RESERVED	R	0h	Reserved
11	SNS_OCP_STD_SHD	R/W	0h	Shutdown type for SNS_OCP faults 0h = Soft shutdown sequence (uses IDRIVENSD) 1h = Standard shutdown sequence (uses IDRIVEN)
10	SNS_OCP_A_EN	R/W	0h	Shunt OCP enable for channel A 0h = Shunt OCP for channel A disabled 1h = Shunt OCP for channel A enabled
9	SNS_OCP_B_EN	R/W	0h	Shunt OCP enable for channel B 0h = Shunt OCP for channel B disabled 1h = Shunt OCP for channel B enabled
8	SNS_OCP_C_EN	R/W	0h	Shunt OCP enable for channel C 0h = Shunt OCP for channel C disabled 1h = Shunt OCP for channel C enabled
7	SNS_OCP_LVL	R/W	0h	Threshold voltage of V_SENSE overcurrent protection (shunt OCP). Threshold is represented as a % of VREF. 0h = 80%/20% of VREF-GND 1h = 90%/10% of VREF-GND
6	RESERVED	R	0h	Reserved
5	SNS_OCP_TRETRY	R/W	0h	Sense OCP retry time 0h = 1ms 1h = 9ms
4-2	SNS_OCP_MODE	R/W	0h	Monitor mode of V_SENSE overcurrent protection (Rshunt monitor) 0h = Warning mode (latched) 1h = Fault mode (latched) 2h = Warning mode (autorecovery) 3h = Fault mode (autorecovery) 4h = Limit mode (autorecovery CBC) 5h = Default mode 6h = Default mode 7h = No report. No shutdown.
1-0	SNS_OCP_DEG	R/W	3h	Deglitch time of V_SENSE overcurrent protection (Rshunt monitor) 0h = 3.0us (typ) 1h = 6.0us (typ) 2h = 9.0us (typ) 3h = 12.0us (typ)

6.7.2.12 MON_CTRL3 Register (Offset = 17h) [Reset = 5101h]

MON_CTRL3 is shown in Table 6-31.

Return to the Summary Table.

Table 6-31 MON_CTRL3 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-14	VDS_MODE	R/W	1h	VDS overcurrent mode 0h = Warning mode (latched) 1h = Fault mode (latched) 2h = Default mode 3h = No report. No shutdown.
13-11	VDS_VGS_BLK	R/W	2h	VDS overcurrent and VGS blanking time 0h = 150ns 1h = 500ns 2h = 1us 3h = 2us 4h = 6us 5h = 8us 6h = 10us 7h = 12us
10-8	VDS_DEG	R/W	1h	VDS overcurrent deglitch time 0h = 500ns 1h = 1us 2h = 1.5us 3h = 2us 4h = 4us 5h = 6us 6h = 8us 7h = 8us
7-6	VGS_MODE	R/W	0h	VGS monitor mode 0h = Warning mode (latched) 1h = Fault mode (latched) 2h = Default mode 3h = No report. No shutdown.
5	RESERVED	R	0h	Reserved
4	RESERVED	R	0h	Reserved
3	RESERVED	R	0h	Reserved
2-0	VGS_DEG	R/W	1h	VGS monitor deglitch time 0h = 500ns 1h = 1us 2h = 1.5us 3h = 2us 4h = 2us 5h = 2us 6h = 2us 7h = 2us

6.7.2.13 MON_CTRL4 Register (Offset = 18h) [Reset = 0000h]

MON_CTRL4 is shown in Table 6-32.

Return to the Summary Table.

Table 6-32 MON_CTRL4 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RESERVED	R	0h	Reserved
14	RESERVED	R	0h	Reserved
13	RESERVED	R	0h	Reserved
12	RESERVED	R	0h	Reserved
11	RESERVED	R	0h	Reserved
10	RESERVED	R	0h	Reserved
9	RESERVED	R	0h	Reserved
8	RESERVED	R	0h	Reserved
7	RESERVED	R	0h	Reserved
6	RESERVED	R	0h	Reserved
5	WDT_FLT_MODE	R/W	0h	Watchdog Time Fault Mode 0h = Warning mode (latched) 1h = Fault mode (latched). Gate Driver shutdown.
4	WDT_CNT	R/W	0h	Watchdog Time Fault Count 0h = One time WDT fault reports status flag and asserts nFAULT1 pin low. 1h = Three consecutive faults report status flag and assert nFAULT pin low. Internal counter is cleared to 0 after the three consecutive faults are detected. Internal counter can also be cleared if WDT_EN is cleared to 0b.
3	WDT_MODE	R/W	0h	Watchdog Time MODE 0h = Any valid read access reset the watchdog timer 1h = A valid write access to CSA_CTRL2 resets the watchdog timer
2-1	WDT_W	R/W	0h	Watchdog Timer window tWDL (lower window) and tWDU (upper window) 0h = tWDL 0.5ms tWDU 10ms 1h = tWDL 1ms tWDU 20ms 2h = tWDL 2ms tWDU 40ms 3h = tWDL 2ms tWDU 40ms
0	WDT_EN	R/W	0h	Watchdog Time Enable 0h = Watchdog timer disabled 1h = Watchdog timer enabled

6.7.2.14 MON_CTRL5 Register (Offset = 19h) [Reset = 0000h]

MON_CTRL5 is shown in Table 6-33.

Return to the Summary Table.

Table 6-33 MON_CTRL5 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RESERVED	R	0h	Reserved
14	RESERVED	R	0h	Reserved
13	RESERVED	R	0h	Reserved
12	RESERVED	R	0h	Reserved
11	RESERVED	R	0h	Reserved
10	RESERVED	R	0h	Reserved
9	RESERVED	R	0h	Reserved
8	RESERVED	R	0h	Reserved
7	RESERVED	R	0h	Reserved
6	DVDD_OV_MODE	R/W	0h	DVDD monitor for overvoltage 0h = Warning mode (latched) 1h = Fault mode (latched)
5-4	VCP_UV_MODE	R/W	0h	VCP monitor mode of under voltage monitor 0h = Warning mode (latched) 1h = Fault mode (latched, TCP ON) 2h = Fault mode (latched, TCP OFF) 3h = No report. No shutdown.
3	BST_UV_LVL	R/W	0h	BST pin undervoltage threshold level V_{BST_UV} 0h = 6.0V (typ) 1h = 5.0V (typ)
2-0	BST_UV_MODE	R/W	0h	BST pin UV monitor mode. 0h = Warning mode (latched) 1h = Fault mode (real time) HS Active PD 2h = Fault mode (real time) HS Weak PD 3h = Fault mode (latched) HS Active PD 4h = Fault mode (latched) HS Weak PD 5h = Fault mode (latched) HS Weak PD, TCP_SW OFF 6h = Default mode 7h = No report. No action.

6.7.2.15 MON_CTRL6 Register (Offset = 1Ah) [Reset = 2000h]

MON_CTRL6 is shown in Table 6-34.

Return to the Summary Table.

Table 6-34 MON_CTRL6 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RESERVED	R	0h	Reserved
14	RESERVED	R	0h	Reserved
13	ALL_CH	R/W	1h	All channel shutdown enable 0h = Associated faulty half-bridge is shutdown (active pull down) in response to VDS, VGS and SNS_OCP. nFAULT goes low after all three channels have the faults. For a recovery sequence to re-start PWM, MCU uses CLR_FLT. 1h = All three half-bridges are shutdown (semi-active pull down) in response to VDS, VGS and SNS_OCP. nFAULT goes low if one or multiple channels have the faults.
12	RESERVED	R	0h	Reserved
11-8	VDS_LVL_A	R/W	0h	VDS overcurrent threshold for phase A 0h = 100mV 1h = 150mV 2h = 200mV 3h = 300mV 4h = 400mV 5h = 500mV 6h = 600mV 7h = 700mV 8h = 800mV 9h = 900mV Ah = 1.0V Bh = 1.5V Ch = 2.0V
7-4	VDS_LVL_B	R/W	0h	VDS overcurrent threshold for phase B 0h = 100mV 1h = 150mV 2h = 200mV 3h = 300mV 4h = 400mV 5h = 500mV 6h = 600mV 7h = 700mV 8h = 800mV 9h = 900mV Ah = 1.0V Bh = 1.5V Ch = 2.0V
3-0	VDS_LVL_C	R/W	0h	VDS overcurrent threshold for phase C 0h = 100mV 1h = 150mV 2h = 200mV 3h = 300mV 4h = 400mV 5h = 500mV 6h = 600mV 7h = 700mV 8h = 800mV 9h = 900mV Ah = 1.0V Bh = 1.5V Ch = 2.0V

6.7.2.16 DIAG_CTRL1 Register (Offset = 1Bh) [Reset = 0000h]

DIAG_CTRL1 is shown in Table 6-35.

Return to the Summary Table.

Table 6-35 DIAG_CTRL1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RESERVED	R	0h	RESERVED
14	RESERVED	R	0h	RESERVED
13	RESERVED	R	0h	RESERVED
12	RESERVED	R	0h	RESERVED
11	OPEN_DET_EN	R/W	0h	Automated offline open load detection. Must be run separately from automated short detection. Bit auto-clears when sequence complete. 0h = Normal operation 1h = Automated open-load detection is enabled
10	SHORT_DET_EN	R/W	0h	Automated offline short detection. Must be run separately from open load detection. Open load detection will be skipped if both open load and short detection are run simultaneously. Bit auto-clears when sequence complete. 0h = Normal operation 1h = Automated short-load detection is enabled
9-8	OFFLINE_DLY	R/W	0h	Automated offline detection delay 0h = 50us (typ) 1h = 250us (typ) 2h = 1ms (typ) 3h = 2.2ms (typ)
7	TCP_LL_MODE	R/W	0h	To reduce TCP_SWITCH current limit for phase diagnostics 0h = Normal TCP_SWITCH current limit 1h = Reduced TCP_SWITCH current limit (230uA, typical)
6	PH_DIAG_LL	R/W	0h	Phase diagnostic low leakage with predriver enabled/disable 0h = PWM'ing allowed during phase diagnostic 1h = No PWM'ing allowed during phase diagnostic
5	PH_DIAG_HA	R/W	0h	Phase diagnostic pull-up enable for phase A 0h = Diagnostic current source disabled 1h = Diagnostic current source enabled
4	PH_DIAG_LA	R/W	0h	Phase diagnostic pull-down enable for phase A 0h = Diagnostic current source disabled 1h = Diagnostic current source enabled
3	PH_DIAG_HB	R/W	0h	Phase diagnostic pull-up enable for phase B 0h = Diagnostic current source disabled 1h = Diagnostic current source enabled
2	PH_DIAG_LB	R/W	0h	Phase diagnostic pull-down enable for phase B 0h = Diagnostic current source disabled 1h = Diagnostic current source enabled
1	PH_DIAG_HC	R/W	0h	Phase diagnostic pull-up enable for phase C 0h = Diagnostic current source disabled 1h = Diagnostic current source enabled
0	PH_DIAG_LC	R/W	0h	Phase diagnostic pull-down enable for phase C 0h = Diagnostic current source disabled 1h = Diagnostic current source enabled

6.7.2.17 IC_CTRL_SP Register (Offset = 1Ch) [Reset = 0805h]

IC_CTRL_SP is shown in Table 6-36.

Return to the Summary Table.

Table 6-36 IC_CTRL_SP Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RESERVED	R	0h	Reserved
14	RESERVED	R	0h	Reserved
13	SPI_CRC_EN	R/W	0h	Enable SPI CRC 0h = No CRC, 24-bit frame 1h = CRC enabled, 32-bit frame
12	DVDD_LVL	R/W	0h	Bit to control LDO output voltage 0h = 3.3V 1h = 5V
11	OTSD_MODE	R/W	1h	Overtemperature shutdown mode 0h = Warning mode (latched) 1h = Fault mode (latched)
10	RESERVED	R	0h	RESERVED
9	RESERVED	R	0h	RESERVED
8	RESERVED	R	0h	RESERVED
7	RESERVED	R	0h	RESERVED
6	RESERVED	R	0h	RESERVED
5	RESERVED	R	0h	RESERVED
4	RESERVED	R	0h	RESERVED
3	RESERVED	R	0h	RESERVED
2-0	LOCK2	R/W	5h	Unlock and lock this register Bit settings not listed have no effect. 2h = Unlock this register 5h = Lock the settings of this register by ignoring further writes except to these bits.