SLVSIM8A June   2025  – December 2025 DRV8363-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Functions 48-Pin DRV8363-Q1
  6. 5 Specification
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Recommended Operating Conditions
    3. 5.3 Thermal Information 1pkg
    4. 5.4 Electrical Characteristics
    5. 5.5 SPI Timing Requirements
    6. 5.6 SPI Timing Diagrams
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Three BLDC Gate Drivers
        1. 6.3.1.1 PWM Control Modes
          1. 6.3.1.1.1 6x PWM Mode
          2. 6.3.1.1.2 3x PWM Mode with INLx enable control
          3. 6.3.1.1.3 1x PWM Mode
        2. 6.3.1.2 Gate Drive Architecture
          1. 6.3.1.2.1 Bootstrap diode
          2. 6.3.1.2.2 VCP Trickle Charge pump
          3. 6.3.1.2.3 Gate Driver Output
          4. 6.3.1.2.4 Passive and Semi-active pull-down resistor
          5. 6.3.1.2.5 TDRIVE/IDRIVE Gate Drive Timing Control
          6. 6.3.1.2.6 Propagation Delay
          7. 6.3.1.2.7 Deadtime and Cross-Conduction Prevention
      2. 6.3.2 DVDD Linear Voltage Regulator
      3. 6.3.3 Low-Side Current Sense Amplifiers
        1. 6.3.3.1 Unidirectional Current Sense Operation
        2. 6.3.3.2 Bidirectional Current Sense Operation
      4. 6.3.4 Gate Driver Shutdown
        1. 6.3.4.1 DRVOFF Gate Driver Shutdown
        2. 6.3.4.2 Soft Shutdown Timing Sequence
      5. 6.3.5 Active Short Circuit
      6. 6.3.6 Gate Driver Protective Circuits
        1. 6.3.6.1  GVDD Undervoltage Lockout (GVDD_UV)
        2. 6.3.6.2  GVDD Overvoltage Fault (GVDD_OV)
        3. 6.3.6.3  VDRAIN Undervoltage Fault (VDRAIN_UV)
        4. 6.3.6.4  VDRAIN Overvoltage Fault (VDRAIN_OV)
        5. 6.3.6.5  VCP Undervoltage Fault (CP_OV)
        6. 6.3.6.6  BST Undervoltage Lockout (BST_UV)
        7. 6.3.6.7  MOSFET VDS Overcurrent Protection (VDS_OCP)
        8. 6.3.6.8  MOSFET VGS Monitoring Protection
        9. 6.3.6.9  Shunt Overcurrent Protection (SNS_OCP)
        10. 6.3.6.10 Thermal Shutdown (OTSD)
        11. 6.3.6.11 Thermal Warning (OTW)
        12. 6.3.6.12 OTP CRC
        13. 6.3.6.13 SPI Watchdog Timer
        14. 6.3.6.14 Phase Diagnostic
    4. 6.4 Fault Detection and Response Summary Table (Fault Table)
    5. 6.5 Device Functional Modes
      1. 6.5.1 Gate Driver Functional Modes
        1. 6.5.1.1 Sleep Mode
        2. 6.5.1.2 Standby Mode
        3. 6.5.1.3 Active Mode
    6. 6.6 Programming
      1. 6.6.1 SPI
      2. 6.6.2 SPI Format
      3. 6.6.3 SPI Format Diagrams
    7. 6.7 Register Maps
      1. 6.7.1 STATUS Registers
      2. 6.7.2 CONTROL Registers
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Typical Application with 48-pin package
        1. 7.2.1.1 External Components
      2. 7.2.2 Application Curves
    3. 7.3 Layout
      1. 7.3.1 Layout Guidelines
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1.     PACKAGE OPTION ADDENDUM
    2. 10.1 Tape and Reel Information

5.4 Electrical Characteristics

Over operating junction temperature range and recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLIES (GVDD, VDRAIN, DVDD)
IVDRAIN_UNPWR VDRAIN sleep current under GVDD unpowered  GVDD = 0V, VDRAIN = 48V, VBST-SH = 0V, nSLEEP=0V, Tj 25C; SH=VDRAIN & 0V
Leakage current of VDRAIN when SH=0V;  Leakage current of VDRAIN+SH when SH=VDRAIN [all 3 predriver phases put together]		 2 4.5 13.5 µA
IGVDD GVDD standby mode current GVDD = 12V, VDRAIN = 48V, INH = INL = 0; DRVOFF = Low, SHx=0V. TCP = ON  No external Load on VCP.  [TCP switches will be toggling] 9.5 13.4 17.5 mA
IGVDD GVDD standby mode current GVDD = 12V, VDRAIN = 48V, INH = INL = 0;  DRVOFF = High, SHx=VDRAIN  TCP = ON No external Load on VCP.   [TCP switches will be ON] 9.7 11.7 17.1 mA
IVDRAIN VDRAIN active mode current GVDD = 12V, VDRAIN = 48V, INH = INL = Switching @ 20kHz; SH=0 when INL=1, SH=VDRAIN when INH=1; SH retains voltage when INH=INL=0; NO FETs connected. TCP is ON,  TCP switches will toggle 4.3 5.2 6.9 mA
IGVDD GVDD active mode current GVDD = 12V, VDRAIN = 48V, INH = INL = Switching @ 20kHz; SH=0 when INL=1, SH=VDRAIN when INH=1; SH retains voltage when INH=INL=0; NO FETs connected. TCP is ON,  TCP switches will toggle 9.8 13.1 20 mA
tWAKE Turnon time GVDD = 12V
nSLEEP = High to active mode (outputs ready) (nFAULT = High)		 10 ms
ILBS_HSPU Bootstrap pin leakage current during high-side pull-up INH = High, SH=VDRAIN=85V; TCP switch off; TDRIVE=0;VBST–SH=12V
.

 		 200 340 450 µA
VDVDD_RT DVDD Digital regulator voltage (Room Temperature) VGVDD ≥  GVDD_UVH, 0 mA ≤ IDVDD ≤ 30 mA external load + 0mA-5mA internal digital load, TJ= 25°C, DVDD_LVL=0 3.23 3.3 3.37 V
VDVDD_RT DVDD Digital regulator voltage (Room Temperature) VGVDD ≥  GVDD_UVH, 30 mA ≤ IDVDD ≤ 100 mA external load + 0mA-5mA internal digital load, TJ= 25°C, DVDD_LVL=0 3.23 3.3 3.37 V
VDVDD DVDD Digital regulator voltage VGVDD ≥  GVDD_UVH, 0 mA ≤ IDVDD ≤ 30 mA external load + 0mA-5mA internal digital load, DVDD_LVL=0 3.21 3.3 3.39 V
VDVDD DVDD Digital regulator voltage VGVDD ≥  GVDD_UVH, 30 mA ≤ IDVDD ≤ 100 mA external load + 0mA-5mA internal digital load, DVDD_LVL=0 3.21 3.3 3.39 V
VDVDD_RT DVDD Digital regulator voltage (Room Temperature) VGVDD ≥  6.5V, 0 mA ≤ IDVDD ≤ 30 mA external load + 0mA-5mA internal digital load, TJ= 25°C, DVDD_LVL=1 4.9 5 5.1 V
VDVDD_RT DVDD Digital regulator voltage (Room Temperature) VGVDD ≥  6.5V, 30 mA ≤ IDVDD ≤ 100 mA external load + 0mA-5mA internal digital load, TJ= 25°C, DVDD_LVL=1 4.9 5 5.1 V
VDVDD DVDD Digital regulator voltage VGVDD ≥  6.5V, 0 mA ≤ IDVDD ≤ 30 mA external load + 0mA-5mA internal digital load, DVDD_LVL=1 4.85 5 5.15 V
VDVDD DVDD Digital regulator voltage VGVDD ≥  6.5V, 30 mA ≤ IDVDD ≤ 100 mA external load + 0mA-5mA internal digital load, DVDD_LVL=1 4.85 5 5.15 V
LOGIC-LEVEL INPUTS (INHx, INLx, nSLEEP, etc.)
VIL Input logic low voltage NSLEEP pin. GVDD>6V 0.8 V
VIL Input logic low voltage DRVOFF pin. GVDD>6V 0.8 V
VIL Input logic low voltage INLx, INHx, ASCIN, SDI, SCLK, nSCS. GVDD>6V 0.8 V
VIH Input logic high voltage NSLEEP pin. GVDD>6V 2.2 V
VIH Input logic high voltage DRVOFF pin. GVDD>6V 2.2 V
VIH Input logic high voltage INLx, INHx, DRVOFF, ASCIN, SDI, SCLK, nSCS GVDD>6V DVDD<4V 2.2 V
VIH Input logic high voltage INLx, INHx, DRVOFF, ASCIN, SDI, SCLK, nSCS GVDD>6V DVDD<5.25V 2.6 V
VIH Input logic high voltage INLx, INHx, DRVOFF, ASCIN, SDI, SCLK, nSCS GVDD>6V DVDD<6V 2.9 V
VOH SDO Voh DVDD > 2.5V; ILOAD=5mA; SDO=H 500 mV
VOL SDO Vol DVDD > 2.5V; ILOAD=5mA; SDO=L 500 mV
VHYS Input hysteresis NSLEEP 100 250 500 mV
VHYS Input hysteresis DRVOFF 50 200 400 mV
VHYS Input hysteresis INLx, INHx, DRVOFF, ASCIN, SDI, SCLK, nSCS 50 200 400 mV
IIL Input logic low current INLx, INHx, DRVOFF, ASCIN, SDI, SCLK = 0V -1 0 1 µA
RPU Input pullup resistance nSCS to DVDD pin 50 100 200 kΩ
RPD Input pulldown resistance SDI, SCLK to GND 50 100 200 kΩ
RPD Input pulldown resistance INLx, INHx, DRVOFF, ASCIN, NSLEEP to GND. 150 250 350 kΩ
tNSLEEP_DG NSLEEP input deglitch time 1 2 4 µs
tDRVOFF_DG DRVOFF input deglitch time 1 2 4 µs
OPEN-DRAIN OUTPUT (nFAULT)
VOL Output logic low voltage IOD = 5 mA, GVDD > 4V 0.4 V
IOZ Output logic high current VOD = 5 V -1 1 µA
BOOTSTRAP DIODE (BST)
VBOOTD Bootstrap diode forward voltage IBOOT = 100 µA 0.82 V
VBOOTD Bootstrap diode forward voltage IBOOT = 10 mA 1 V
VBOOTD Bootstrap diode forward voltage IBOOT = 100 mA 1.6 V
RBOOTD Bootstrap dynamic resistance (ΔVBOOTD/ΔIBOOT) IBOOT = 100 mA and 50 mA 3.9 4.8 9 Ω
TRICKLE CHARGE PUMP (VCP)
VTCP Trickle charge pump output voltage VVCP-VDRAIN , VDRAIN > 15V, GVDD>11V, VDRAIN>GVDD+4V; External load IVCP < 4mA 10.3 10.7 10.9 V
VTCP Trickle charge pump output voltage VVCP-VDRAIN , VDRAIN > 15V, 8V<GVDD<11V, VDRAIN>GVDD+4V; External load IVCP < 2mA 7.5 7.8 8.0 V
Trickle charge pump output voltage VVCP-VDRAIN , VDRAIN=GVDD, 8V<GVDD<11V, External load IVCP < 2mA 4.0 5.4 6.7 V
VBST_TCPOFF BST monitor voltage for VCP to stop charging the BST cap (rising voltage) INLx = 0; SHx = 0, VDRAIN; VDRAIN =  48V, 85V 12.0 13.2 14.6 V
TPRECHARGE Startup time for bootstrap precharge INH=INL=0; BST_UVLO=highest level; TCP_SWITCH=PRECHARGE mode (5mA); GVDD > 11V, VDRAIN > GVDD + 4V; SHx=VDRAIN; 1.5 3 ms
ITCP_NRM VCP to BST switch current; normal mode BST=SH=0; VCP>15V; TCP_HD_DIS=1; TCP_SW_CURLIM=0; 1.25 mA
ITCP_NRM VCP to BST switch current; normal mode BST=SH=0; VCP>15V; TCP_HD_DIS=1; TCP_SW_CURLIM=1; 2.3 mA
ITCP_PCHG VCP to BST switch current; Precharge mode BST=SH=0; VCP>15V; 5.2 mA
ITCP_HD VCP to BST switch current; high duty cycle mode with TCP_SW_HD_CURLIM=0b00 BST=SH=0; VCP>15V; TCP_HD_DIS=0b; TCP_SW_HD_CURLIM=0b00; 7.7 mA
ITCP_HD VCP to BST switch current; high duty cycle mode  with TCP_SW_HD_CURLIM=0b01 BST=SH=0; VCP>15V; TCP_HD_DIS=0b; TCP_SW_HD_CURLIM=0b01; 6.4 mA
ITCP_HD VCP to BST switch current; high duty cycle mode  with TCP_SW_HD_CURLIM=0b10 BST=SH=0; VCP>15V; TCP_HD_DIS=0b; TCP_SW_HD_CURLIM=0b10; 10.5 mA
ITCP_HD VCP to BST switch current; high duty cycle mode  with TCP_SW_HD_CURLIM=0b11 BST=SH=0; VCP>15V; TCP_HD_DIS=0b; TCP_SW_HD_CURLIM=0b11; 9.2 mA
GATE DRIVERS (GH, GL, SH, SL)
VGSHx_LO High-side gate drive low level voltage (VGH - VSH) IGHx = -10 mA; VGVDD = 12V; IDRIVE = 1000mA, No FETs connected 0 0.022 0.2 V
VGSHx_HI High-side gate drive high level voltage (VBST - VGH) IGHx = 10 mA; VGVDD = 12V; IDRIVE = 500mA, No FETs connected 0 0.09 0.2 V
VGSLx_LO Low-side gate drive low level voltage (VGL - VSL) IGLx = -10 mA; VGVDD = 12V; IDRIVE = 1000mA, No FETs connected 0 0.022 0.2 V
VGSLx_HI Low-side gate drive high level voltage (VGVDD - VGL) IGLx = 10 mA; VGVDD = 12V; IDRIVE = 500mA,  No FETs connected 0 0.09 0.2 V
IDRIVEP0 Peak source gate current VBST-VSH = VGVDD = 12V, IDRVP_xx = 0x0 9 16 26 mA
IDRIVEP1 VBST-VSH = VGVDD = 12V, IDRVP_xx = 0x1 19 32 52 mA
IDRIVEP2 VBST-VSH = VGVDD = 12V, IDRVP_xx = 0x2 38 64 103 mA
IDRIVEP3 VBST-VSH = VGVDD = 12V, IDRVP_xx = 0x3 57 96 154 mA
IDRIVEP4 VBST-VSH = VGVDD = 12V, IDRVP_xx = 0x4 76 128 205 mA
IDRIVEP5 VBST-VSH = VGVDD = 12V, IDRVP_xx = 0x5 96 160 256 mA
IDRIVEP6 VBST-VSH = VGVDD = 12V, IDRVP_xx = 0x6 115 192 308 mA
IDRIVEP7 VBST-VSH = VGVDD = 12V, IDRVP_xx = 0x7 134 224 359 mA
IDRIVEP8 VBST-VSH = VGVDD = 12V, IDRVP_xx = 0x8 153 256 410 mA
IDRIVEP9 VBST-VSH = VGVDD = 12V, IDRVP_xx = 0x9 172 288 461 mA
IDRIVEP10 VBST-VSH = VGVDD = 12V, IDRVP_xx = 0xA 192 320 512 mA
IDRIVEP11 VBST-VSH = VGVDD = 12V, IDRVP_xx = 0xB 230 384 615 mA
IDRIVEP12 VBST-VSH = VGVDD = 12V, IDRVP_xx = 0xC 307 512 820 mA
IDRIVEP13 VBST-VSH = VGVDD = 12V, IDRVP_xx = 0xD 460 768 1229 mA
IDRIVEP14 VBST-VSH = VGVDD = 12V, IDRVP_xx = 0xE 614 1024 1639 mA
IDRIVEP15 VBST-VSH = VGVDD = 12V,, IDRVP_xx = 0xF 614 1024 1639 mA
IDRIVEN0 Peak sink gate current VBST-VSH = VGVDD = 12V, IDRVN_xx = 0x0 19 32 52 mA
IDRIVEN1 VBST-VSH = VGVDD = 12V, IDRVN_xx = 0x1 38 64 103 mA
IDRIVEN2 VBST-VSH = VGVDD = 12V, IDRVN_xx = 0x2 76 128 205 mA
IDRIVEN3 VBST-VSH = VGVDD = 12V, IDRVN_xx = 0x3 115 192 308 mA
IDRIVEN4 VBST-VSH = VGVDD = 12V, IDRVN_xx = 0x4 153 256 410 mA
IDRIVEN5 VBST-VSH = VGVDD = 12V, IDRVN_xx = 0x5 192 320 512 mA
IDRIVEN6 VBST-VSH = VGVDD = 12V, IDRVN_xx = 0x6 230 384 615 mA
IDRIVEN7 VBST-VSH = VGVDD = 12V, IDRVN_xx = 0x7 268 448 717 mA
IDRIVEN8 VBST-VSH = VGVDD = 12V, IDRVN_xx = 0x8 307 512 820 mA
IDRIVEN9 VBST-VSH = VGVDD = 12V, IDRVN_xx = 0x9 345 576 922 mA
IDRIVEN10 VBST-VSH = VGVDD = 12V, IDRVN_xx = 0xA 384 640 1024 mA
IDRIVEN11 VBST-VSH = VGVDD = 12V, IDRVN_xx = 0xB 460 768 1229 mA
IDRIVEN12 VBST-VSH = VGVDD = 12V, IDRVN_xx = 0xC 614 1024 1639 mA
IDRIVEN13 VBST-VSH = VGVDD = 12V, IDRVN_xx = 0xD 921 1536 2458 mA
IDRIVEN14 VBST-VSH = VGVDD = 12V, IDRVN_xx = 0xE 1228 2048 3277 mA
IDRIVEN15 VBST-VSH = VGVDD = 12V, IDRVN_xx = 0xF 1228 2048 3277 mA
RPD_LS Low-side passive pull down GL to SL, VGL - VSL = 2V 60 85 120 kΩ
RPDSA_HS High-side semiactive pull down GVDD_UV = 1
GH to SH, VGH - VSH = 2V
 2 4 8 kΩ
IPUHOLD_L High-side pull-up hold low current IHOLD_SEL = 0 614 1024 1639 mA
IPUHOLD_H High-side pull-up hold high current IHOLD_SEL = 1 153 256 410 mA
IPDSTRONG_LS Low-side pull-down strong current 1228 2048 3277 mA
IPDSTRONG_HS High-side pull-down strong current 1228 2048 3277 mA
GATE DRIVERS TIMINGS
tPDR_LS Low-side rising propagation delay INL to GL rising, VGVDD > 8V 45 63 90 ns
tPDF_LS Low-side falling propagation delay INL to GL falling, VGVDD > 8V 45 64 90 ns
tPDR_HS High-side rising propagation delay INH to GH rising, VGVDD = VBST - VSH > 8V
 45 62 90 ns
tPDF_HS High-side falling propagation delay INH to GH falling, VGVDD = VBST - VSH > 8V
 45 65 90 ns
tPD_MATCH Matching propagation delay of low-side gate driver GL turning ON to GL turning OFF, From VGL-SL = 1V to VGL-SL = VGVDD - 1V;  VGVDD = VBST - VSH > 8V; VSH = 0V to 90V, no load on GH and GL -8 ±4 8 ns
Matching propagation delay of high-side gate driver GH turning ON to GH turning OFF, From VGH-SH = 1V to VGH-SH = VBST-SH - 1V;  VGVDD = VBST - VSH > 8V; VSH = 0V to 90V, no load on GH and GL -10 ±4 10 ns
tPD_MATCH_PH Matching propagation delay per phase Deadtime disabled. GL turning OFF to GH turning ON, From VGL-SL = VGVDD - 1V to VGH-SH = 1V; VGVDD = VBST - VSH > 8V; VSH = 0V to 90V, no load on GH and GL, dead time disabled -12 ±4 12 ns
Deadtime disabled. GH turning OFF to GL turning ON, From VGH-SH = VBST-SH - 1V to VGL-SL = 1V ; VGVDD = VBST - VSH > 8V; VSH = 0V to 90V, no load on GH and GL -11 ±4 11 ns
tDEAD Digital gate drive dead time DEADT = 0000b = 0h 70 ns
tDEAD Digital gate drive dead time DEADT = 0001b = 1h 120 ns
tDEAD Digital gate drive dead time DEADT = 0010b = 2h 180 ns
tDEAD Digital gate drive dead time DEADT = 0011b = 3h 300 ns
tDEAD Digital gate drive dead time DEADT = 0100b = 4h 400 ns
tDEAD Digital gate drive dead time DEADT = 0101b = 5h 500 ns
tDEAD Digital gate drive dead time DEADT = 0110b = 6h 600 ns
tDEAD Digital gate drive dead time DEADT = 0111b = 7h 750 ns
tDEAD Digital gate drive dead time DEADT = 1000b = 8h 1000 ns
tDEAD Digital gate drive dead time DEADT = 1001b = 9h 1.5 us
tDEAD Digital gate drive dead time DEADT = 1010b = Ah 2 us
tDEAD Digital gate drive dead time DEADT = 1011b = Bh 2.5 us
tDEAD Digital gate drive dead time DEADT = 1100b = Ch 3 us
tDEAD Digital gate drive dead time DEADT = 1101b = Dh 3.5 us
tDEAD Digital gate drive dead time DEADT = 1110b = Eh 5 us
tDEAD Digital gate drive dead time DEADT = 1111b = Fh 10 us
tDEAD Analog propagation delay dead time variation Inserted on top of digital deadtime -12 4 12 ns
CURRENT SHUNT AMPLIFIERS (SNx, SOx, SPx, VREF)
ACSA Sense amplifier gain CSAGAIN = 00b 5 V/V
CSAGAIN = 01b 10 V/V
CSAGAIN = 10b 20 V/V
CSAGAIN = 11b 40 V/V
ACSA Sense amplifier gain CSAGAIN = 00b 4.9 5 5.08 V/V
CSAGAIN = 01b 9.85 10 10.15 V/V
CSAGAIN = 10b 19.7 20 20.3 V/V
CSAGAIN = 11b 39.4 40 40.8 V/V
ACSA_ERR_DRIFT Sense amplifier gain error temperature drift -30 30 ppm/℃
NL Non linearity Error 0.01 0.05 %
tSET Settling time to ±1% VSTEP = 1.6 V, ACSA = 5 V/V, CSO = 500pF; VREF=4.5V-5.5V; k=1/2; Cboardroute=0pF-60pF 0.6 1.6 µs
VSTEP = 1.6 V, ACSA = 10 V/V, CSO = 500pF; VREF=4.5V-5.5V; k=1/2; Cboardroute=0pF-60pF 0.65 1.6 µs
VSTEP = 1.6 V, ACSA = 20 V/V, CSO = 500pF; VREF=4.5V-5.5V; k=1/2; Cboardroute=0pF-60pF 0.7 1.6 µs
VSTEP = 1.6 V, ACSA = 40 V/V, CSO = 500pF; VREF=4.5V-5.5V; k=1/2; Cboardroute=0pF-60pF 1.25 2.1 µs
tSET Settling time to ±1% VSTEP = 1.6 V, ACSA = 5 V/V, CSO = 60pF ; VREF=4.5V-5.5V; k=1/2; Cboardroute=0pF-60pF 0.3 0.6 µs
VSTEP = 1.6 V, ACSA = 10 V/V, CSO = 60pF; VREF=4.5V-5.5V; k=1/2; Cboardroute=0pF-60pF 0.35 0.6 µs
VSTEP = 1.6 V, ACSA = 20 V/V, CSO = 60pF; VREF=4.5V-5.5V; k=1/2; Cboardroute=0pF-60pF 0.35 0.7 µs
VSTEP = 1.6 V, ACSA = 40 V/V, CSO = 60pF; VREF=4.5V-5.5V; k=1/2; Cboardroute=0pF-60pF 0.6 0.9 µs
BW Bandwidth ACSA = 5 V/V, CLOAD = 60-pF, small signal -3 dB 3 5 7 MHz
ACSA = 10 V/V, CLOAD = 60-pF, small signal -3 dB 2.5 4.8 6.6 MHz
ACSA = 20 V/V, CLOAD = 60-pF, small signal -3 dB 2 4 5.4 MHz
ACSA = 40 V/V, CLOAD = 60-pF, small signal -3 dB 1.75 3 4.2 MHz
tSR Output slew rate VSTEP = 1.6 V, ACSA = 5 V/V, CLOAD = 60-pF, low to high transition 14 V/µs
VSTEP = 1.6 V, ACSA = 10 V/V, CLOAD = 60-pF, low to high transition 13 V/µs
VSTEP = 1.6 V, ACSA = 20 V/V, CLOAD = 60-pF, low to high transition 13 V/µs
VSTEP = 1.6 V, ACSA = 40 V/V, CLOAD = 60-pF, low to high transition 6 V/µs
VSWING Output voltage range VVREF = 3

 0.25 2.75 V
VSWING Output voltage range VVREF = 5.5

 0.25 5.25 V
VSWING Output voltage range VVREF = 3 to 5.5 V

 0.25 VVREF - 0.25 V
VCOM Common-mode input range -0.15 0.15 V
VDIFF Differential-mode input range Gain ACSA = 5 V/V

 -0.3 0.3 V
VOFF Input offset voltage VSP = VSN = GND; TJ = -40℃, G=5V/V
 -2.65 2.65 mV
VOFF Input offset voltage VSP = VSN = GND; TJ = -40℃, G=10, 20, 40V/V
 -1.5 1.5 mV
VOFF Input offset voltage VSP = VSN = GND; TJ = 25℃, G=5V/V
 -2.65 2.65 mV
VOFF Input offset voltage VSP = VSN = GND; TJ = 25℃, G=10, 20, 40V/V
 -1.5 1.5 mV
VOFF Input offset voltage VSP = VSN = GND; TJ = 150℃, G=5V/V
 -2.65 2.65 mV
VOFF Input offset voltage VSP = VSN = GND; TJ = 150℃, G=10, 20, 405V/V
 -1.5 1.5 mV
VOFF Input offset voltage VSP = VSN = GND;G=5V/V
 -2.6 2.6 mV
VOFF_DRIFT Input drift offset voltage VSP = VSN = GND
 -10 0 10 µV/℃
VBIAS Output voltage bias ratio VSP = VSN = GND 0.5
VBIAS_ACC Outpu voltage bias ratio accuracy -1.2 1.8 %
IBIAS Input bias current VSP = VSN = GND, VVREF = 3V to 5.5V 100 µA
IBIAS_OFF Input bias current offset ISP – ISN -2.5 2.5 µA
CMRR Common-mode rejection ratio DC 80 dB
20 kHz 60 dB
PSRR Power-supply rejection ratio GVDD to SOx, DC 100 dB
PSRR Power-supply rejection ratio GVDD to SOx, 20 kHz 63 dB
PSRR Power-supply rejection ratio (VREF) VREF to SOx, DC, Differential 85 dB
VREF to SOx, 20 kHz, Differential 90 dB
PSRR Power-supply rejection ratio (VREF) VREF to SOx, 20 kHz, Single Ended 40 dB
ICSA_SUP Supply leakage current for CSA during GVDD unpowered VREF, VVREF = 3.V to 5.5V, GVDD = 0V, VDRAIN = 48V / 0V 1000 nA
ICSA_SUP Supply current for CSA VREF, VVREF = 3.V to 5.5V 4.5 6.5 mA
TCMREC Common mode recovery time 2 2.5 us
RIPPLE SOx output ripple voltage Peak to peak , VREF = 3 to 5.5V, SOx cap = 500pf, Input refered, SOx/ GAIN 850 1100 uV
CLOAD Maximum load capacitance 10 nF
PROTECTION CIRCUITS
VGVDD_UV_BST GVDD undervoltage warning threshold rising GVDD_UV_BST_LV = 1b 9.25 9.6 9.95 V
VGVDD_UV_BST GVDD undervoltage warning threshold falling GVDD_UV_BST_LVL = 1b 9.1 9.45 9.8 V
VGVDD_UV_BST GVDD undervoltage warning threshold rising GVDD_UV_BST_LVL = 0b 10.25 10.65 10.95 V
VGVDD_UV_BST GVDD undervoltage warning threshold falling GVDD_UV_BST_LVL = 0b 10.1 10.45 10.8 V
VGVDD_UVH GVDD undervoltage fault threshold rising 7.2 7.55 7.9 V
VGVDD_UVH GVDD undervoltage fault threshold falling 7 7.35 7.7 V
VGVDD_UVLO GVDD undervoltage lockout threshold 5.35 5.65 5.95 V
VGVDD_UVLO GVDD undervoltage lockout threshold 5.25 5.55 5.85 V
VGVDD_OV GVDD overvoltage threshold rising 16.9 17.65 18.4 V
VGVDD_OV GVDD overvoltage threshold falling 16.5 17.25 18 V
tGVDD_UVOV_DEG GVDD under/overvoltage deglitch 12 µs
VVDRAIN_UVH VDRAIN undervoltage fault threshold rising VDRAIN_UVH_LVL = 0b 18 19 20 V
VVDRAIN_UVH VDRAIN undervoltage fault threshold falling VDRAIN_UVH_LVL = 0b 17 18 19 V
VVDRAIN_UVH VDRAIN undervoltage fault threshold rising VDRAIN_UVH_LVL = 01b 20 21 22 V
VVDRAIN_UVH VDRAIN undervoltage fault threshold falling VDRAIN_UVH_LVL = 01b 19 20 21 V
VVDRAIN_UVH VDRAIN undervoltage fault threshold rising VDRAIN_UVH_LVL = 10b 22 23 24 V
VVDRAIN_UVH VDRAIN undervoltage fault threshold falling VDRAIN_UVH_LVL = 10b  21 22 23 V
VVDRAIN_UVH VDRAIN undervoltage fault threshold rising VDRAIN_UVH_LVL = 11b 24 25 26 V
VVDRAIN_UVH VDRAIN undervoltage fault threshold falling VDRAIN_UVH_LVL = 11b 23 24 25 V
VVDRAIN_UVL VDRAIN undervoltage threshold to disable TCP rising VDRAIN_UVL_LVL = 0b 10.2 10.7 11.2
VVDRAIN_UVL VDRAIN undervoltage threshold to disable TCP falling VDRAIN_UVL_LVL = 0b 10 10.5 11 V
VVDRAIN_UVL VDRAIN undervoltage threshold to disable TCP rising VDRAIN_UVL_LVL = 1b 5.15 5.65 5.95 V
VVDRAIN_UVL VDRAIN undervoltage threshold to disable TCP falling VDRAIN_UVL_LVL = 1b 5.05 5.55 5.85 V
tVDRAIN_UV_DEG VDRAIN undervoltage deglitch 12 µs
VVDRAIN_OV VDRAIN overvoltage fault threshold rising VDRAIN_OV_LVL = 0b.  55.5 58 60.5 V
VVDRAIN_OV VDRAIN overvoltage fault threshold falling VDRAIN_OV_LVL = 0b.  53.5 56 58.5 V
VVDRAIN_OV VDRAIN overvoltage fault threshold rising VDRAIN_OV_LVL = 1b.  57.5 60 62.5 V
VVDRAIN_OV VDRAIN overvoltage fault threshold falling VDRAIN_OV_LVL = 1b.  55.5 58 60.5 V
VVDRAIN_OV VDRAIN overvoltage fault threshold rising VDRAIN_OV_LVL = 10b.  59.5 62 64.5 V
VVDRAIN_OV VDRAIN overvoltage fault threshold falling VDRAIN_OV_LVL = 10b.  57.5 60 62.5 V
VVDRAIN_OV VDRAIN overvoltage fault threshold rising VDRAIN_OV_LVL = 11b.  78 81.5 84 V
VVDRAIN_OV VDRAIN overvoltage fault threshold falling VDRAIN_OV_LVL = 11b.  76 79.5 82 V
tVDRAIN_OV_DEG VDRAIN overvoltage deglitch 6.5 µs
VVCP_UV VCP undervoltage fault threshold rising 6.7 7.6 8.4 V
VVCP_UV VCP undervoltage fault threshold falling 6.5 7.4 8.2 V
tVCP_UV_DEG VCP undervoltage deglitch 12 µs
VBST_UV_HI Bootstrap undervoltage level (high) rising 8V < GVDD < 9V; PREDRV_BST_UVLO=1 4.5 5.15 5.8 V
VBST_UV_HI Bootstrap undervoltage level (high) falling 8V < GVDD < 9V; PREDRV_BST_UVLO=1 4.4 5.05 5.7 V
VBST_UV_LO Bootstrap undervoltage level (low) rising GVDD > 9V; PREDRV_BST_UVLO=0 5.45 6.1 6.8 V
VBST_UV_LO Bootstrap undervoltage level (low) falling GVDD > 9V; PREDRV_BST_UVLO=0 5.35 6 6.65 V
tBST_UV_DEG Bootstrap undervoltage deglitch 6 µs
VDVDD_UV DVDD undervoltage fault threshold rising 2.6 2.75 2.9 V
VDVDD_UV DVDD undervoltage fault threshold falling 2.5 2.65 2.8 V
VDVDD_OV DVDD overvoltage fault threshold rising DVDD_LDO_SEL = 0b (3.3V) 3.7 3.85 4.0 V
VDVDD_OV DVDD overvoltage fault threshold falling DVDD_LDO_SEL = 0b (3.3V) 3.65 3.8 3.95 V
VDVDD_OV DVDD overvoltage fault threshold rising DVDD_LDO_SEL = 1b (5V) 5.55 5.75 5.95 V
VDVDD_OV DVDD overvoltage fault threshold falling DVDD_LDO_SEL = 1b (5V) 5.5 5.7 5.9 V
tDVDD_OV_DEG DVDD overvoltage deglitch 18 µs
VVREF_UV VREF undervoltage fault threshold rising VREF Rising 2.05 2.2 2.35 V
VVREF_UV VREF undervoltage fault threshold falling VREF falling 1.85 2 2.15 V
tVREF_UV_DEG VREF undervoltage deglitch 12 µs
TOTW Overtemperature warning threshold rising 127 142 157 °C
TOTW Overtemperature warning threshold falling 121 136 151 °C
TOTSD Overtemperature shutdown threshold rising 161 176 191 °C
TOTSD Overtemperature shutdown threshold falling 155 170 185 °C
VVDS_LVL0 VDS overcurrent fault level VDS_LVL_x = 0000b 0.075 0.1 0.120 V
VVDS_LVL1 VDS overcurrent fault level VDS_LVL_x = 0001b 0.125 0.15 0.170 V
VVDS_LVL2 VDS overcurrent fault level VDS_LVL_x = 0010b 0.175 0.2 0.220 V
VVDS_LVL3 VDS overcurrent fault level VDS_LVL_x = 0011b 0.27 0.3 0.33 V
VVDS_LVL4 VDS overcurrent fault level VDS_LVL_x = 0100b 0.38 0.4 0.42 V
VVDS_LVL5 VDS overcurrent fault level VDS_LVL_x = 0101b 0.475 0.5 0.525 V
VVDS_LVL6 VDS overcurrent fault level VDS_LVL_x = 0110b 0.57 0.6 0.63 V
VVDS_LVL7 VDS overcurrent fault level VDS_LVL_x = 0111b 0.67 0.7 0.73 V
VVDS_LVL8 VDS overcurrent fault level VDS_LVL_x = 1000b 0.76 0.8 0.84 V
VVDS_LVL9 VDS overcurrent fault level VDS_LVL_x = 1001b 0.86 0.9 0.94 V
VVDS_LVL10 VDS overcurrent fault level VDS_LVL_x = 1010b 0.95 1.0 1.05 V
VVDS_LVL11 VDS overcurrent fault level VDS_LVL_x = 1011b 1.43 1.5 1.57 V
VVDS_LVL12 VDS overcurrent fault level VDS_LVL_x = 1100b 1.9 2.0 2.1 V
VVGS_FLT VGS fault threshold rising Fault VGS monitor mode. VGS rising

 0.6 1.2 1.7 V
VVGS_FLT VGS fault threshold falling Fault VGS monitor mode. VGS falling

 0.5 1.1 1.6 V
tVGS_DG0 VGS fault programmable deglitch VGS_DEG = 00b 0.5 µs
tVGS_DG1 VGS fault programmable deglitch VGS_DEG = 01b 1.0 µs
tVGS_DG2 VGS fault programmable deglitch VGS_DEG = 10b 1.5 µs
tVGS_DG3 VGS fault programmable deglitch VGS_DEG = 11b 2.0 µs
tBLNK0 VDS/VGS monitoring programmable blanking period VDS_VGS_BLK = 000b 0 µs
tBLNK1 VDS/VGS monitoring programmable blanking period VDS_VGS_BLK = 001b 0.5 µs
tBLNK2 VDS/VGS monitoring programmable blanking period VDS_VGS_BLK = 010b 1.0 µs
tBLNK3 VDS/VGS monitoring programmable blanking period VDS_VGS_BLK = 011b 2.0 µs
tBLNK4 VDS/VGS monitoring programmable blanking period VDS_VGS_BLK = 100b 6.0 µs
tBLNK5 VDS/VGS monitoring programmable blanking period VDS_VGS_BLK = 101b 8.0 µs
tBLNK6 VDS/VGS monitoring programmable blanking period VDS_VGS_BLK = 110b 10.0 µs
tBLNK7 VDS/VGS monitoring programmable blanking period VDS_VGS_BLK = 111b 12.0 µs
tVDS_DG0 VDS protection deglitch time  VDS_DEG = 000b 0.5 µs
tVDS_DG1 VDS protection deglitch time  VDS_DEG = 001b 1.0 µs
tVDS_DG2 VDS protection deglitch time  VDS_DEG = 010b 1.5 µs
tVDS_DG3 VDS protection deglitch time  VDS_DEG = 011b 2.0 µs
tVDS_DG4 VDS protection deglitch time  VDS_DEG = 100b 4.0 µs
tVDS_DG5 VDS protection deglitch time  VDS_DEG = 101b 6.0 µs
tVDS_DG6 VDS protection deglitch time  VDS_DEG = 110b, 111b 8.0 µs
Trip_Drift Aging drift of LS and HS VDS thresholds -2 0 2 mV
IOPENLOAD_PU Open  load pullup current on SH pin 2.4 3.5 6 mA
IOPENLOAD_PD Open  load pulldown current on SH pin 2.4 4.2 6 mA
RSHUNT_OCP
VRSHUNT_OCP SNS_OCP threshold RSHUNT_OCP_LVL=0 VREF*0.20 VREF*0.80
VRSHUNT_OCP SNS_OCP threshold RSHUNT_OCP_LVL=1 VREF*0.10 VREF*0.90
RSHUNT_OCP_VAR SNS_OCP threshold variation RSHUNT_OCP_LVL=0,1, k=1/2, SN/SP Common mode =0V -3.2 3.2 %
RSHUNT_OCP_VAR SNS_OCP threshold variation RSHUNT_OCP_LVL=0,1, k=1/2, SN/SP Common mode =-0.175V -3.5 3.5 %
RSHUNT_OCP_VAR SNS_OCP threshold variation RSHUNT_OCP_LVL=0,1, k=1/2, SN/SP Common mode =0.7V -3.8 3.8 %
RSHUNT_OCP_VAR SNS_OCP threshold variation RSHUNT_OCP_LVL=0,1, k=1/8, SN/SP Common mode =0V -2 2 %
RSHUNT_OCP_VAR SNS_OCP threshold variation RSHUNT_OCP_LVL=0,1, k=1/8, SN/SP Common mode =-0.175V -2 2 %
RSHUNT_OCP_VAR SNS_OCP threshold variation RSHUNT_OCP_LVL=0,1, k=1/8, SN/SP Common mode =0.7V -2 2 %
tSNS_OCP_DEG SNS_OCP Deglitch SNS_OCP_DEG = 00b 3 µs
tSNS_OCP_DEG SNS_OCP Deglitch SNS_OCP_DEG = 01b 6 µs
tSNS_OCP_DEG SNS_OCP Deglitch SNS_OCP_DEG = 10b 9 µs
tSNS_OCP_DEG SNS_OCP Deglitch SNS_OCP_DEG = 11b 12 µs