SLVSIM8A June   2025  – December 2025 DRV8363-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Functions 48-Pin DRV8363-Q1
  6. 5 Specification
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Recommended Operating Conditions
    3. 5.3 Thermal Information 1pkg
    4. 5.4 Electrical Characteristics
    5. 5.5 SPI Timing Requirements
    6. 5.6 SPI Timing Diagrams
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Three BLDC Gate Drivers
        1. 6.3.1.1 PWM Control Modes
          1. 6.3.1.1.1 6x PWM Mode
          2. 6.3.1.1.2 3x PWM Mode with INLx enable control
          3. 6.3.1.1.3 1x PWM Mode
        2. 6.3.1.2 Gate Drive Architecture
          1. 6.3.1.2.1 Bootstrap diode
          2. 6.3.1.2.2 VCP Trickle Charge pump
          3. 6.3.1.2.3 Gate Driver Output
          4. 6.3.1.2.4 Passive and Semi-active pull-down resistor
          5. 6.3.1.2.5 TDRIVE/IDRIVE Gate Drive Timing Control
          6. 6.3.1.2.6 Propagation Delay
          7. 6.3.1.2.7 Deadtime and Cross-Conduction Prevention
      2. 6.3.2 DVDD Linear Voltage Regulator
      3. 6.3.3 Low-Side Current Sense Amplifiers
        1. 6.3.3.1 Unidirectional Current Sense Operation
        2. 6.3.3.2 Bidirectional Current Sense Operation
      4. 6.3.4 Gate Driver Shutdown
        1. 6.3.4.1 DRVOFF Gate Driver Shutdown
        2. 6.3.4.2 Soft Shutdown Timing Sequence
      5. 6.3.5 Active Short Circuit
      6. 6.3.6 Gate Driver Protective Circuits
        1. 6.3.6.1  GVDD Undervoltage Lockout (GVDD_UV)
        2. 6.3.6.2  GVDD Overvoltage Fault (GVDD_OV)
        3. 6.3.6.3  VDRAIN Undervoltage Fault (VDRAIN_UV)
        4. 6.3.6.4  VDRAIN Overvoltage Fault (VDRAIN_OV)
        5. 6.3.6.5  VCP Undervoltage Fault (CP_OV)
        6. 6.3.6.6  BST Undervoltage Lockout (BST_UV)
        7. 6.3.6.7  MOSFET VDS Overcurrent Protection (VDS_OCP)
        8. 6.3.6.8  MOSFET VGS Monitoring Protection
        9. 6.3.6.9  Shunt Overcurrent Protection (SNS_OCP)
        10. 6.3.6.10 Thermal Shutdown (OTSD)
        11. 6.3.6.11 Thermal Warning (OTW)
        12. 6.3.6.12 OTP CRC
        13. 6.3.6.13 SPI Watchdog Timer
        14. 6.3.6.14 Phase Diagnostic
    4. 6.4 Fault Detection and Response Summary Table (Fault Table)
    5. 6.5 Device Functional Modes
      1. 6.5.1 Gate Driver Functional Modes
        1. 6.5.1.1 Sleep Mode
        2. 6.5.1.2 Standby Mode
        3. 6.5.1.3 Active Mode
    6. 6.6 Programming
      1. 6.6.1 SPI
      2. 6.6.2 SPI Format
      3. 6.6.3 SPI Format Diagrams
    7. 6.7 Register Maps
      1. 6.7.1 STATUS Registers
      2. 6.7.2 CONTROL Registers
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Typical Application with 48-pin package
        1. 7.2.1.1 External Components
      2. 7.2.2 Application Curves
    3. 7.3 Layout
      1. 7.3.1 Layout Guidelines
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1.     PACKAGE OPTION ADDENDUM
    2. 10.1 Tape and Reel Information

4 Pin Functions 48-Pin DRV8363-Q1

DRV8363-Q1 DRV8363-Q1 Package 48-Pin QFN With Exposed Thermal Pad Top View Figure 4-1 DRV8363-Q1 Package 48-Pin QFN With Exposed Thermal Pad Top View
Table 4-1 Pin Functions (48-QFN)
PINI/O(1)DESCRIPTION
NAMENO.
GLC1OLow-side gate driver output. Connect to the gate of the low-side power MOSFET.
SLC2ILow-side source sense input. Connect to the low-side power MOSFET source.
SPA3ILow-side current shunt amplifier input. Connect to the low-side power MOSFET source and high-side of the current shunt resistor.
SNA4ICurrent sense amplifier input. Connect to the low-side of the current shunt resistor.
SPB5ILow-side current shunt amplifier input. Connect to the low-side power MOSFET source and high-side of the current shunt resistor.
SNB6ICurrent sense amplifier input. Connect to the low-side of the current shunt resistor.
SPC7ILow-side current shunt amplifier input. Connect to the low-side power MOSFET source and high-side of the current shunt resistor.
SNC8ICurrent sense amplifier input. Connect to the low-side of the current shunt resistor.
DRVOFF9IActive high shutdown input to pull-down gate driver outputs GHx and GLx.
AGND10PWRDevice ground.
INHA11IHigh-side gate driver control input. This pin controls the output of the high-side gate driver.
INLA12ILow-side gate driver control input. This pin controls the output of the low-side gate driver.
INHB13IHigh-side gate driver control input. This pin controls the output of the high-side gate driver.
INLB14ILow-side gate driver control input. This pin controls the output of the low-side gate driver.
INHC15IHigh-side gate driver control input. This pin controls the output of the high-side gate driver.
INLC16ILow-side gate driver control input. This pin controls the output of the low-side gate driver.
SDO17OSerial data output.
SDI18ISerial data input.
SCLK19ISerial clock input.
nSCS20ISerial chip select.
nSLEEP21IGate driver nSLEEP. When this pin is logic low the device goes to a low-power sleep mode.
nFAULT22ODFault indicator output. This pin is pulled logic low during a fault condition and requires an external pullup resistor.
VREF23PWRExternal voltage reference for current sense amplifiers.
SOC24OCurrent sense amplifier output.
SOB25OCurrent sense amplifier output.
SOA26OCurrent sense amplifier output.
GND27PWRDevice ground
DVDD28PWR3.3V / 5V LDO output. Connect to adjacent GND with a >10V-rated ceramic capacitor.
ASCIN29IASC external trigger pin. When this pin is logic high, the device turns on all three low-side or high-side gates.
GVDD30PWRGate driver power supply input. Connect an externally regulated 8V-15V supply with a GVDD-rated ceramic between the GVDD and GND pins.
NC31NCNot connected. Leave pin floating.
CPTL32PWRTrickle charge pump switching node. Connect a charge pump flying capacitor between CPTL and CPTH pins.
CPTH33PWRTrickle charge pump switching node. Connect a charge pump flying capacitor between CPTL and CPTH pins.
VCP34PWRTrickle charge pump storage capacitor. Connect a ceramic capacitor between VCP and VDRAIN pins.
VDRAIN35PWRHigh-side drain sense and charge pump power supply input.
BSTA36OBootstrap output pin. Connect a bootstrap capacitor between BSTA and SHA
SHA37IHigh-side source sense input. Connect to the high-side power MOSFET source.
GHA38OHigh-side gate driver output. Connect to the gate of the high-side power MOSFET.
GLA39OLow-side gate driver output. Connect to the gate of the low-side power MOSFET.
SLA40ILow-side source sense input. Connect to the low-side power MOSFET source.
SLB41ILow-side source sense input. Connect to the low-side power MOSFET source.
GLB42OLow-side gate driver output. Connect to the gate of the low-side power MOSFET.
GHB43OHigh-side gate driver output. Connect to the gate of the high-side power MOSFET.
SHB44IHigh-side source sense input. Connect to the high-side power MOSFET source.
BSTB45OBootstrap output pin. Connect a bootstrap capacitor between BSTB and SHB
BSTC46OBootstrap output pin. Connect a bootstrap capacitor between BSTC and SHC
SHC47IHigh-side source sense input. Connect to the high-side power MOSFET source.
GHC48OHigh-side gate driver output. Connect to the gate of the high-side power MOSFET.
(1) Signal Types: I = Input, O = Output, I/O = Input or Output., PWR = Power