SLVSL35 September   2026 TUSB2514B

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Battery Charging Features
      2. 6.3.2 USB Power Management
      3. 6.3.3 Clock Generation
        1. 6.3.3.1 Crystal Requirements
        2. 6.3.3.2 Input Clock Requirements
      4. 6.3.4 Power-Up and Reset
    4. 6.4 Device Functional Modes
      1. 6.4.1 I2C EEPROM Operation
      2. 6.4.2 SMBus Target Operation
      3. 6.4.3 Port Configuration
  8. 7 Register Maps
    1. 7.1 TUSB2514 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 TUSB2514B Power Supply
      2. 8.3.2 Downstream Port Power
      3. 8.3.3 Ground
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Placement
        2. 8.4.1.2 Package Specific
        3. 8.4.1.3 Differential Pairs
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

8.4.1.3 Differential Pairs

This section describes the layout recommendations for all the TUSB2514B device differential pairs: USB_DP_XX, USB_DM_XX.

  • The differential pairs must be designed with a differential impedance of 90 Ω ± 10%.
  • To minimize crosstalk, TI recommends to keep high-speed signals away from each other. Separate each pair by at least 5 times the signal trace width. Separating with ground as depicted in the layout example also helps minimize crosstalk.
  • Route all differential pairs on the same layer adjacent to a solid ground plane.
  • Do not route differential pairs over any plane split.
  • Adding test points causes impedance discontinuity and therefore negatively impacts signal performance. If test points are used, place them in series and symmetrically. Do not place them in a manner that causes stub on the differential pair.
  • Avoid 90° turns in trace. Keep the use of bends in differential traces to a minimum. When bends are used, make sure the number of left and right bends are as equal as possible and that the angle of the bend is ≥135°. This guideline minimizes any length mismatch caused by the bends and therefore minimize the impact bends have on EMI.
  • Minimize the trace lengths of the differential pair traces. Eight inches is the maximum recommended trace length for USB 2.0 differential pair signals. Longer trace lengths require very careful routing to ensure proper signal integrity.
  • Match the etch lengths of the differential pair traces (that is DP and DM). Make sure the USB 2.0 differential pairs do not exceed 50 mils relative trace length difference.
  • Minimize the use of vias in the differential pair paths as much as possible. If this is not practical, make sure that the same via type and placement are used for both signals in a pair. Place any vias used as close as possible to the TUSB2514B device.
  • To ease routing of the USB 2.0 DP and DM pair, the polarity of these pins can be swapped. If this is done, set the appropriate Px_usb2pol register, where x = 0, 1, 2, 3, or 4.
  • Do not place power fuses across the differential pair traces.