SLVSL35 September   2026 TUSB2514B

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Battery Charging Features
      2. 6.3.2 USB Power Management
      3. 6.3.3 Clock Generation
        1. 6.3.3.1 Crystal Requirements
        2. 6.3.3.2 Input Clock Requirements
      4. 6.3.4 Power-Up and Reset
    4. 6.4 Device Functional Modes
      1. 6.4.1 I2C EEPROM Operation
      2. 6.4.2 SMBus Target Operation
      3. 6.4.3 Port Configuration
  8. 7 Register Maps
    1. 7.1 TUSB2514 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 TUSB2514B Power Supply
      2. 8.3.2 Downstream Port Power
      3. 8.3.3 Ground
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Placement
        2. 8.4.1.2 Package Specific
        3. 8.4.1.3 Differential Pairs
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

5.6 Timing Requirements

MIN NOM MAX UNIT
Power-on timings.
tsu_io Setup for MISC inputs. (1) Sampled at the deassertion of GRSTz 0.1 µs
thd_io Hold for MISC inputs. (1) Sampled at the deassertion of GRSTz 0.1 µs
tVDD33_RAMP VDD33 supply ramp requirement. 0.2 100 ms
(1) MISC pins sampled at deassertion of GRST#: BATEN[4:1]