SNVSCB5B March   2022  – May 2025 TPS388R0-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 I2C
      2. 7.3.2 Auto Mask (AMSK)
      3. 7.3.3 PEC
      4. 7.3.4 VDD
      5. 7.3.5 MON
      6. 7.3.6 NIRQ
      7. 7.3.7 NRST
    4. 7.4 Device Functional Modes
      1. 7.4.1 Built-In Self Test and Configuration Load
        1. 7.4.1.1 Notes on BIST Execution
      2. 7.4.2 TPS38800-Q1 Power ON
      3. 7.4.3 General Monitoring
        1. 7.4.3.1 IDLE Monitoring
        2. 7.4.3.2 ACTIVE Monitoring
        3. 7.4.3.3 Sequence Monitoring 1
          1. 7.4.3.3.1 ACT Transitions 0→1
          2. 7.4.3.3.2 SLEEP Transition 1→0
          3. 7.4.3.3.3 SLEEP Transition 0→1
        4. 7.4.3.4 Sequence Monitoring 2
          1. 7.4.3.4.1 ACT Transition 1→0
    5. 7.5 Register Maps
      1. 7.5.1 Registers Overview
        1. 7.5.1.1 BANK0 Registers
        2. 7.5.1.2 BANK1 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Multichannel Sequencer and Monitor
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
      4. 8.2.4 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Supply Guidelines
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Nomenclature
    2. 9.2 Documentation Support
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

7.5.1.2 BANK1 Registers

Table 7-38 lists the memory-mapped registers for the BANK1 registers. All register offset addresses not listed in Table 7-38 should be considered as reserved locations and the register contents should not be modified.

Table 7-38 BANK1 Registers
OffsetAcronymBit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
10hVMON_CTLRESERVEDRESET_PROTRESERVEDFORCE_NIRQ_LOW
11hVMON_MISCRESERVEDREQ_PECEN_PEC
12hTEST_CFGRESERVEDAT_SHDNAT_POR[1]AT_POR[0]
13hIEN_UVHFMON[8]MON[7]MON[6]MON[5]MON[4]MON[3]MON[2]MON[1]
15hIEN_OVHFMON[8]MON[7]MON[6]MON[5]MON[4]MON[3]MON[2]MON[1]
1BhIEN_CONTROLRESERVEDRT_CRC_IntRESERVEDTSD_INTRESERVEDPEC_INT
1ChIEN_TESTRESERVEDECC_SECRESERVEDBIST_Complete_INTBIST_Fail_INT
1DhIEN_VENDORStartup Self-Test_CRCRESERVEDNRST_MISMATCHRESERVED
1EhMON_CH_ENMON[8]MON[7]MON[6]MON[5]MON[4]MON[3]MON[2]MON[1]
1FhVRANGE_MULTMON[8]MON[7]MON[6]MON[5]MON[4]MON[3]MON[2]MON[1]
20hUV_HF[1]THRESHOLD[7:0]
21hOV_HF[1]THRESHOLD[7:0]
24hFLT_HF[1]OV_DEB[3:0]UV_DEB[3:0]
25hFC_LF[1]RESERVEDOVHF_TO_NRSTUVHF_TO_NRSTRESERVED
30hUV_HF[2]THRESHOLD[7:0]
31hOV_HF[2]THRESHOLD[7:0]
34hFLT_HF[2]OV_DEB[3:0]UV_DEB[3:0]
35hFC_LF[2]RESERVEDOVHF_TO_NRSTUVHF_TO_NRSTRESERVED
40hUV_HF[3]THRESHOLD[7:0]
41hOV_HF[3]THRESHOLD[7:0]
44hFLT_HF[3]OV_DEB[3:0]UV_DEB[3:0]
45hFC_LF[3]RESERVEDOVHF_TO_NRSTUVHF_TO_NRSTRESERVED
50hUV_HF[4]THRESHOLD[7:0]
51hOV_HF[4]THRESHOLD[7:0]
54hFLT_HF[4]OV_DEB[3:0]UV_DEB[3:0]
55hFC_LF[4]RESERVEDOVHF_TO_NRSTUVHF_TO_NRSTRESERVED
60hUV_HF[5]THRESHOLD[7:0]
61hOV_HF[5]THRESHOLD[7:0]
64hFLT_HF[5]OV_DEB[3:0]UV_DEB[3:0]
65hFC_LF[5]RESERVEDOVHF_TO_NRSTUVHF_TO_NRSTRESERVED
70hUV_HF[6]THRESHOLD[7:0]
71hOV_HF[6]THRESHOLD[7:0]
74hFLT_HF[6]OV_DEB[3:0]UV_DEB[3:0]
75hFC_LF[6]RESERVEDOVHF_TO_NRSTUVHF_TO_NRSTRESERVED
80hUV_HF[7]THRESHOLD[7:0]
81hOV_HF[7]THRESHOLD[7:0]
84hFLT_HF[7]OV_DEB[3:0]UV_DEB[3:0]
85hFC_LF[7]RESERVEDOVHF_TO_NRSTUVHF_TO_NRSTRESERVED
90hUV_HF[8]THRESHOLD[7:0]
91hOV_HF[8]THRESHOLD[7:0]
94hFLT_HF[8]OV_DEB[3:0]UV_DEB[3:0]
95hFC_LF[8]RESERVEDOVHF_TO_NRSTUVHF_TO_NRSTRESERVED
9FhTI_CONTROLENTER_BISTRESERVEDI2C_MRRESERVEDRST_DLY[2:0]
A1hAMSK_ONMON[8]MON[7]MON[6]MON[5]MON[4]MON[3]MON[2]RESERVED
A2hAMSK_OFFMON[8]MON[7]MON[6]MON[5]MON[4]MON[3]MON[2]MON[1]
A3hAMSK_EXSMON[8]MON[7]MON[6]MON[5]MON[4]MON[3]MON[2]MON[1]
A4hAMSK_ENSMON[8]MON[7]MON[6]MON[5]MON[4]MON[3]MON[2]MON[1]
F0hBANK_SELRESERVEDBANK_Select

Complex bit access types are encoded to fit into small table cells. Table 7-39 shows the codes that are used for access types in this section.

Table 7-39 BANK1 Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

5.1.2.1 VMON_CTL Register (Offset = 10h) [Reset = X0h]

VMON_CTL is shown in Table 7-40.

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VMON device control register.

Table 7-40 VMON_CTL Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR0h Reserved
3RESET_PROTR/WXh Reset_Prot = read 0, write 1 to clear Protection registers
2-1RESERVEDR0h Reserved
0FORCE_NIRQ_LOWR/WXh Force assertion of NIRQ

5.1.2.2 VMON_MISC Register (Offset = 11h) [Reset = X0h]

VMON_MISC is shown in Table 7-41.

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Miscellaneous VMON configurations.

Table 7-41 VMON_MISC Register Field Descriptions
BitFieldTypeResetDescription
7-2RESERVEDR0h Reserved
1REQ_PECR/WXh Require PEC.
0 = PEC not required
1 = PEC required
0EN_PECR/WXh Enable PEC.
0 = PEC not enabled
1 = PEC enabled

5.1.2.3 TEST_CFG Register (Offset = 12h) [Reset = X0h]

TEST_CFG is shown in Table 7-42.

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Built-In Self Test (BIST) execution configuration.

Table 7-42 TEST_CFG Register Field Descriptions
BitFieldTypeResetDescription
7-3RESERVEDR0h Reserved
2AT_SHDNR/WXh Run BIST at SHDN
1AT_POR[1]R/WXh Run BIST at POR, 2nd bit for redundancy
0AT_POR[0]R/WXh Run BIST at POR

5.1.2.4 IEN_UVHF Register (Offset = 13h) [Reset = X0h]

IEN_UVHF is shown in Table 7-43.

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High Frequency channel Under-Voltage Interrupt Enable register

Table 7-43 IEN_UVHF Register Field Descriptions
BitFieldTypeResetDescription
7MON[8]R/W0h UVHF interrupt enable for MON8,
0 = Disable,
1 = Enable
6MON[7]R/W0h UVHF interrupt enable for MON7,
0 = Disable,
1 = Enable
5MON[6]R/W0h UVHF interrupt enable for MON6,
0 = Disable,
1 = Enable
4MON[5]R/W0h UVHF interrupt enable for MON5,
0 = Disable,
1 = Enable
3MON[4]R/WXh UVHF interrupt enable for MON4,
0 = Disable,
1 = Enable
2MON[3]R/WXh UVHF interrupt enable for MON3,
0 = Disable,
1 = Enable
1MON[2]R/WXh UVHF interrupt enable for MON2,
0 = Disable,
1 = Enable
0MON[1]R/WXh UVHF interrupt enable for MON1,
0 = Disable,
1 = Enable

5.1.2.5 IEN_OVHF Register (Offset = 15h) [Reset = X0h]

IEN_OVHF is shown in Table 7-44.

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High Frequency channel Over-Voltage Interrupt Enable register.

Table 7-44 IEN_OVHF Register Field Descriptions
BitFieldTypeResetDescription
7MON[8]R/W0h OVHF interrupt enable for MON8,
0 = Disable,
1 = Enable
6MON[7]R/W0h OVHF interrupt enable for MON7,
0 = Disable,
1 = Enable
5MON[6]R/W0h OVHF interrupt enable for MON6,
0 = Disable,
1 = Enable
4MON[5]R/W0h OVHF interrupt enable for MON5,
0 = Disable,
1 = Enable
3MON[4]R/WXh OVHF interrupt enable for MON4,
0 = Disable,
1 = Enable
2MON[3]R/WXh OVHF interrupt enable for MON3,
0 = Disable,
1 = Enable
1MON[2]R/WXh OVHF interrupt enable for MON2,
0 = Disable,
1 = Enable
0MON[1]R/WXh OVHF interrupt enable for MON1,
0 = Disable,
1 = Enable

5.1.2.6 IEN_CONTROL Register (Offset = 1Bh) [Reset = X0h]

IEN_CONTROL is shown in Table 7-45.

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Control and Communication Fault Interrupt Enable register.

Table 7-45 IEN_CONTROL Register Field Descriptions
BitFieldTypeResetDescription
7-5RESERVEDR0h Reserved
4RT_CRC_IntR/W0h Register Run time CRC (Cyclic Redundancy Checking) error Interrupt is a static CRC perfomed on the register map content. If enabled there does not need to be any data read or write for this CRC check to occur. The puropose of this CRC is to identify if a static bit flip or random error in the register map content has occured. This is the safety mechanism is carried out using a CRC-8 polynomial, in the case of a read or write operation the register map content changes and the polynomial is re-calculated with the new value after the changes. Interrupt is reported in INT_CONTROL_F_CRC register of Bank 0.
0 = Disable Interrupt Mapping,
1 = Enable Interrupt Mapping
3RESERVEDR0h Reserved
2TSD_INTR/WXh Thermal shutdown Interrupt.
0 = Disable,
1 = Enable
1RESERVEDR0h Reserved
0PEC_INTR/WXh PEC Error Interrupt.
0 = Disable,
1 = Enable

5.1.2.7 IEN_TEST Register (Offset = 1Ch) [Reset = X0h]

IEN_TEST is shown in Table 7-46.

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Internal Test and Configuration Load Fault Interrupt Enable register

Table 7-46 IEN_TEST Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR0h Reserved
3ECC_SECR/WXh SEC Error Interrupt.
0 = Disable,
1 = Enable
2RESERVEDR0h Reserved
1BIST_Complete_INTR/WXh BIST complete Interrupt.
0 = Disable,
1 = Enable
0BIST_Fail_INTR/WXh BIST Fail Interrupt.
0 = Disable,
Enable = 1

5.1.2.8 IEN_VENDOR Register (Offset = 1Dh) [Reset = X0h]

IEN_VENDOR is shown in Table 7-47.

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Vendor Specific Internal Interrupt Enable register.

Table 7-47 IEN_VENDOR Register Field Descriptions
BitFieldTypeResetDescription
7Startup Self-Test_CRCR/W0h Startup Self-Test_CRC Interrupt.
0 = Disable Interrupt Mapping,
1 = Enable Interrupt Mapping
6RESERVEDR0h Reserved
5NRST_MISMATCHR/W0h NRST mismatch Interrupt.
0 = Disable Interrupt Mapping,
1 = Enable Interrupt Mapping
4-0RESERVEDR0h Reserved

5.1.2.9 MON_CH_EN Register (Offset = 1Eh) [Reset = X0h]

MON_CH_EN is shown in Table 7-48.

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Channel Voltage Monitoring Enable.

Table 7-48 MON_CH_EN Register Field Descriptions
BitFieldTypeResetDescription
7MON[8]R/W0h Enables MON8 monitoring.
0 = Disabled,
1 = Enabled
6MON[7]R/W0h Enables MON7 monitoring.
0 = Disabled,
1 = Enabled
5MON[6]R/W0h Enables MON6 monitoring.
0 = Disabled,
1 = Enabled
4MON[5]R/W0h Enables MON5 monitoring.
0 = Disabled,
1 = Enabled
3MON[4]R/WXh Enables MON4 monitoring.
0 = Disabled,
1 = Enabled
2MON[3]R/WXh Enables MON3 monitoring.
0 = Disabled,
1 = Enabled
1MON[2]R/WXh Enables MON2 monitoring.
0 = Disabled,
1 = Enabled
0MON[1]R/WXh Enables MON1 monitoring.
0 = Disabled,
1 = Enabled

5.1.2.10 VRANGE_MULT Register (Offset = 1Fh) [Reset = X0h]

VRANGE_MULT is shown in Table 7-49.

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Channel Voltage Monitoring Range/Scaling.

Table 7-49 VRANGE_MULT Register Field Descriptions
BitFieldTypeResetDescription
7MON[8]R/W0h Scalar for MON8.
0 = 1x,
1 = 4x
6MON[7]R/W0h Scalar for MON7.
0 = 1x,
1 = 4x
5MON[6]R/W0h Scalar for MON6.
0 = 1x,
1 = 4x
4MON[5]R/W0h Scalar for MON5.
0 = 1x,
1 = 4x
3MON[4]R/WXh Scalar for MON4.
0 = 1x,
1 = 4x
2MON[3]R/WXh Scalar for MON3.
0 = 1x,
1 = 4x
1MON[2]R/WXh Scalar for MON2.
0 = 1x,
1 = 4x
0MON[1]R/WXh Scalar for MON1.
0 = 1x,
1 = 4x

5.1.2.11 UV_HF[1] Register (Offset = 20h) [Reset = X0h]

UV_HF[1] is shown in Table 7-50.

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Channel 1 High Frequency channel Under-Voltage threshold.

Table 7-50 UV_HF[1] Register Field Descriptions
BitFieldTypeResetDescription
7-0THRESHOLD[7:0]R/WXh Undervoltage threshold for High Frequency component of monitored channel.
The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT.
With scaling = 1x, the 8-bit value represents the range 0.2V to 1.475V
with 1 LSB = 5mV.
With scaling = 4x, the 8-bit value represents the range 0.8V to 5.9V with 1 LSB = 20mV.

5.1.2.12 OV_HF[1] Register (Offset = 21h) [Reset = X0h]

OV_HF[1] is shown in Table 7-51.

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Channel 1 High Frequency channel Over-Voltage threshold.

Table 7-51 OV_HF[1] Register Field Descriptions
BitFieldTypeResetDescription
7-0THRESHOLD[7:0]R/WXh Overvoltage threshold for High Frequency component of monitored channel.
The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT.
With scaling = 1x, the 8-bit value represents the range 0.2V to 1.475V
with 1 LSB = 5mV.
With scaling = 4x, the 8-bit value represents the range 0.8V to 5.9V with 1 LSB = 20mV.

5.1.2.13 FLT_HF[1] Register (Offset = 24h) [Reset = X0h]

FLT_HF[1] is shown in Table 7-52.

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Channel 1 UV and OV debouncing for High Frequency thresholds comparator output.

Table 7-52 FLT_HF[1] Register Field Descriptions
BitFieldTypeResetDescription
7-4OV_DEB[3:0]R/W0h Overvoltage comparator output debounce time (dont assert until output is stable for debounce time) for High Frequency monitoring path.
0000b = 0.1µs 1000b = 25.6µs
0001b = 0.2µs 1001b = 51.2µs
0010b = 0.4µs 1010b = 102.4µs
0011b = 0.8µs 1011b = 102.4µs
0100b = 1.6µs 1100b = 102.4µs
0101b = 3.2µs 1101b = 102.4µs
0110b = 6.4µs 1110b = 102.4µs
0111b = 12.8µs 1111b = 102.4µs
3-0UV_DEB[3:0]R/WXh Undervoltage comparator output debounce time (dont assert until output is stable for debounce time) for High Frequency monitoring path.
0000b = 0.1µs 1000b = 25.6µs
0001b = 0.2µs 1001b = 51.2µs
0010b = 0.4µs 1010b = 102.4µs
0011b = 0.8µs 1011b = 102.4µs
0100b = 1.6µs 1100b = 102.4µs
0101b = 3.2µs 1101b = 102.4µs
0110b = 6.4µs 1110b = 102.4µs
0111b = 12.8µs 1111b = 102.4µs

5.1.2.14 FC_LF[1] Register (Offset = 25h) [Reset = X0h]

FC_LF[1] is shown in Table 7-53.

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Channel 1 UV and OV mapping to NRST error output

Table 7-53 FC_LF[1] Register Field Descriptions
BitFieldTypeResetDescription
7-5RESERVEDR0h Reserved
4OVHF_TO_NRSTR/W0h Maps MON1 OVHF fault to NRST
0 = Not mapped,
1 = Mapped
3UVHF_TO_NRSTR/WXh Maps MON1 UVHF fault to NRST
0 = Not mapped,
1 = Mapped
2-0RESERVEDR0h Reserved

5.1.2.15 UV_HF[2] Register (Offset = 30h) [Reset = X0h]

UV_HF[2] is shown in Table 7-54.

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Channel 2 High Frequency channel Under-Voltage threshold.

Table 7-54 UV_HF[2] Register Field Descriptions
BitFieldTypeResetDescription
7-0THRESHOLD[7:0]R/WXh Undervoltage threshold for High Frequency component of monitored channel.
The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT.
With scaling = 1x, the 8-bit value represents the range 0.2V to 1.475V
with 1 LSB = 5mV.
With scaling = 4x, the 8-bit value represents the range 0.8V to 5.9V with 1 LSB = 20mV.

5.1.2.16 OV_HF[2] Register (Offset = 31h) [Reset = X0h]

OV_HF[2] is shown in Table 7-55.

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Channel 2 High Frequency channel Over-Voltage threshold.

Table 7-55 OV_HF[2] Register Field Descriptions
BitFieldTypeResetDescription
7-0THRESHOLD[7:0]R/WXh Overvoltage threshold for High Frequency component of monitored channel.
The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT.
With scaling = 1x, the 8-bit value represents the range 0.2V to 1.475V
V with 1 LSB = 5mV.
With scaling = 4x, the 8-bit value represents the range 0.8V to 5.9V with 1 LSB = 20mV.

5.1.2.17 FLT_HF[2] Register (Offset = 34h) [Reset = X0h]

FLT_HF[2] is shown in Table 7-56.

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Channel 2 UV and OV debouncing for High Frequency thresholds comparator output.

Table 7-56 FLT_HF[2] Register Field Descriptions
BitFieldTypeResetDescription
7-4OV_DEB[3:0]R/W0h Overvoltage comparator output debounce time (dont assert until output is stable for debounce time) for High Frequency monitoring path.
0000b = 0.1µs 1000b = 25.6µs
0001b = 0.2µs 1001b = 51.2µs
0010b = 0.4µs 1010b = 102.4µs
0011b = 0.8µs 1011b = 102.4µs
0100b = 1.6µs 1100b = 102.4µs
0101b = 3.2µs 1101b = 102.4µs
0110b = 6.4µs 1110b = 102.4µs
0111b = 12.8µs 1111b = 102.4µs
3-0UV_DEB[3:0]R/WXh Undervoltage comparator output debounce time (dont assert until output is stable for debounce time) for High Frequency monitoring path.
0000b = 0.1µs 1000b = 25.6µs
0001b = 0.2µs 1001b = 51.2µs
0010b = 0.4µs 1010b = 102.4µs
0011b = 0.8µs 1011b = 102.4µs
0100b = 1.6µs 1100b = 102.4µs
0101b = 3.2µs 1101b = 102.4µs
0110b = 6.4µs 1110b = 102.4µs
0111b = 12.8µs 1111b = 102.4µs

5.1.2.18 FC_LF[2] Register (Offset = 35h) [Reset = X0h]

FC_LF[2] is shown in Table 7-57.

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Channel 2 UV and OV mapping to NRST error output

Table 7-57 FC_LF[2] Register Field Descriptions
BitFieldTypeResetDescription
7-5RESERVEDR0h Reserved
4OVHF_TO_NRSTR/W0h Maps MON2 OVHF fault to NRST
0 = Not mapped,
1 = Mapped
3UVHF_TO_NRSTR/WXh Maps MON2 UVHF fault to NRST
0 = Not mapped,
1 = Mapped
2-0RESERVEDR0h Reserved

5.1.2.19 UV_HF[3] Register (Offset = 40h) [Reset = X0h]

UV_HF[3] is shown in Table 7-58.

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Channel 3 High Frequency channel Under-Voltage threshold.

Table 7-58 UV_HF[3] Register Field Descriptions
BitFieldTypeResetDescription
7-0THRESHOLD[7:0]R/WXh Undervoltage threshold for High Frequency component of monitored channel.
The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT.
With scaling = 1x, the 8-bit value represents the range 0.2V to 1.475V
with 1 LSB = 5mV.
With scaling = 4x, the 8-bit value represents the range 0.8V to 5.9V with 1 LSB = 20mV.

5.1.2.20 OV_HF[3] Register (Offset = 41h) [Reset = X0h]

OV_HF[3] is shown in Table 7-59.

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Channel 3 High Frequency channel Over-Voltage threshold.

Table 7-59 OV_HF[3] Register Field Descriptions
BitFieldTypeResetDescription
7-0THRESHOLD[7:0]R/WXh Overvoltage threshold for High Frequency component of monitored channel.
The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT.
With scaling = 1x, the 8-bit value represents the range 0.2V to 1.475V
with 1 LSB = 5mV.
With scaling = 4x, the 8-bit value represents the range 0.8V to 5.9V with 1 LSB = 20mV.

5.1.2.21 FLT_HF[3] Register (Offset = 44h) [Reset = X0h]

FLT_HF[3] is shown in Table 7-60.

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Channel 3 UV and OV debouncing for High Frequency thresholds comparator output.

Table 7-60 FLT_HF[3] Register Field Descriptions
BitFieldTypeResetDescription
7-4OV_DEB[3:0]R/W0h Overvoltage comparator output debounce time (dont assert until output is stable for debounce time) for High Frequency monitoring path.
0000b = 0.1µs 1000b = 25.6µs
0001b = 0.2µs 1001b = 51.2µs
0010b = 0.4µs 1010b = 102.4µs
0011b = 0.8µs 1011b = 102.4µs
0100b = 1.6µs 1100b = 102.4µs
0101b = 3.2µs 1101b = 102.4µs
0110b = 6.4µs 1110b = 102.4µs
0111b = 12.8µs 1111b = 102.4µs
3-0UV_DEB[3:0]R/WXh Undervoltage comparator output debounce time (dont assert until output is stable for debounce time) for High Frequency monitoring path.
0000b = 0.1µs 1000b = 25.6µs
0001b = 0.2µs 1001b = 51.2µs
0010b = 0.4µs 1010b = 102.4µs
0011b = 0.8µs 1011b = 102.4µs
0100b = 1.6µs 1100b = 102.4µs
0101b = 3.2µs 1101b = 102.4µs
0110b = 6.4µs 1110b = 102.4µs
0111b = 12.8µs 1111b = 102.4µs

5.1.2.22 FC_LF[3] Register (Offset = 45h) [Reset = X0h]

FC_LF[3] is shown in Table 7-61.

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Channel 3 UV and OV mapping to NRST error output

Table 7-61 FC_LF[3] Register Field Descriptions
BitFieldTypeResetDescription
7-5RESERVEDR0h Reserved
4OVHF_TO_NRSTR/W0h Maps MON3 OVHF fault to NRST
0 = Not mapped,
1 = Mapped
3UVHF_TO_NRSTR/WXh Maps MON3 UVHF fault to NRST
0 = Not mapped,
1 = Mapped
2-0RESERVEDR0h Reserved

5.1.2.23 UV_HF[4] Register (Offset = 50h) [Reset = X0h]

UV_HF[4] is shown in Table 7-62.

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Channel 4 High Frequency channel Under-Voltage threshold.

Table 7-62 UV_HF[4] Register Field Descriptions
BitFieldTypeResetDescription
7-0THRESHOLD[7:0]R/WXh Undervoltage threshold for High Frequency component of monitored channel.
The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT.
With scaling = 1x, the 8-bit value represents the range 0.2V to 1.475V
with 1 LSB = 5mV.
With scaling = 4x, the 8-bit value represents the range 0.8V to 5.9V with 1 LSB = 20mV.

5.1.2.24 OV_HF[4] Register (Offset = 51h) [Reset = X0h]

OV_HF[4] is shown in Table 7-63.

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Channel 4 High Frequency channel Over-Voltage threshold.

Table 7-63 OV_HF[4] Register Field Descriptions
BitFieldTypeResetDescription
7-0THRESHOLD[7:0]R/WXh Overvoltage threshold for High Frequency component of monitored channel.
The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT.
With scaling = 1x, the 8-bit value represents the range 0.2V to 1.475V
with 1 LSB = 5mV.
With scaling = 4x, the 8-bit value represents the range 0.8V to 5.9V with 1 LSB = 20mV.

5.1.2.25 FLT_HF[4] Register (Offset = 54h) [Reset = X0h]

FLT_HF[4] is shown in Table 7-64.

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Channel 4 UV and OV debouncing for High Frequency thresholds comparator output.

Table 7-64 FLT_HF[4] Register Field Descriptions
BitFieldTypeResetDescription
7-4OV_DEB[3:0]R/W0h Overvoltage comparator output debounce time (dont assert until output is stable for debounce time) for High Frequency monitoring path.
0000b = 0.1µs 1000b = 25.6µs
0001b = 0.2µs 1001b = 51.2µs
0010b = 0.4µs 1010b = 102.4µs
0011b = 0.8µs 1011b = 102.4µs
0100b = 1.6µs 1100b = 102.4µs
0101b = 3.2µs 1101b = 102.4µs
0110b = 6.4µs 1110b = 102.4µs
0111b = 12.8µs 1111b = 102.4µs
3-0UV_DEB[3:0]R/WXh Undervoltage comparator output debounce time (dont assert until output is stable for debounce time) for High Frequency monitoring path.
0000b = 0.1µs 1000b = 25.6µs
0001b = 0.2µs 1001b = 51.2µs
0010b = 0.4µs 1010b = 102.4µs
0011b = 0.8µs 1011b = 102.4µs
0100b = 1.6µs 1100b = 102.4µs
0101b = 3.2µs 1101b = 102.4µs
0110b = 6.4µs 1110b = 102.4µs
0111b = 12.8µs 1111b = 102.4µs

5.1.2.26 FC_LF[4] Register (Offset = 55h) [Reset = X0h]

FC_LF[4] is shown in Table 7-65.

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Channel 4 UV and OV mapping to NRST error output

Table 7-65 FC_LF[4] Register Field Descriptions
BitFieldTypeResetDescription
7-5RESERVEDR0h Reserved
4OVHF_TO_NRSTR/W0h Maps MON4 OVHF fault to NRST
0 = Not mapped,
1 = Mapped
3UVHF_TO_NRSTR/WXh Maps MON4 UVHF fault to NRST
0 = Not mapped,
1 = Mapped
2-0RESERVEDR0h Reserved

5.1.2.27 UV_HF[5] Register (Offset = 60h) [Reset = X0h]

UV_HF[5] is shown in Table 7-66.

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Channel 5 High Frequency channel Under-Voltage threshold.

Table 7-66 UV_HF[5] Register Field Descriptions
BitFieldTypeResetDescription
7-0THRESHOLD[7:0]R/WXh Undervoltage threshold for High Frequency component of monitored channel.
The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT.
With scaling = 1x, the 8-bit value represents the range 0.2V to 1.475
V with 1 LSB = 5mV.
With scaling = 4x, the 8-bit value represents the range 0.8V to 5.9V with 1 LSB = 20mV.

5.1.2.28 OV_HF[5] Register (Offset = 61h) [Reset = X0h]

OV_HF[5] is shown in Table 7-67.

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Channel 5 High Frequency channel Over-Voltage threshold.

Table 7-67 OV_HF[5] Register Field Descriptions
BitFieldTypeResetDescription
7-0THRESHOLD[7:0]R/WXh Overvoltage threshold for High Frequency component of monitored channel.
The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT.
With scaling = 1x, the 8-bit value represents the range 0.2V to 1.475
V with 1 LSB = 5mV.
With scaling = 4x, the 8-bit value represents the range 0.8V to 5.9V with 1 LSB = 20mV.

5.1.2.29 FLT_HF[5] Register (Offset = 64h) [Reset = X0h]

FLT_HF[5] is shown in Table 7-68.

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Channel 5 UV and OV debouncing for High Frequency thresholds comparator output.

Table 7-68 FLT_HF[5] Register Field Descriptions
BitFieldTypeResetDescription
7-4OV_DEB[3:0]R/W0h Overvoltage comparator output debounce time (dont assert until output is stable for debounce time) for High Frequency monitoring path.
0000b = 0.1µs 1000b = 25.6µs
0001b = 0.2µs 1001b = 51.2µs
0010b = 0.4µs 1010b = 102.4µs
0011b = 0.8µs 1011b = 102.4µs
0100b = 1.6µs 1100b = 102.4µs
0101b = 3.2µs 1101b = 102.4µs
0110b = 6.4µs 1110b = 102.4µs
0111b = 12.8µs 1111b = 102.4µs
3-0UV_DEB[3:0]R/WXh Undervoltage comparator output debounce time (dont assert until output is stable for debounce time) for High Frequency monitoring path.
0000b = 0.1µs 1000b = 25.6µs
0001b = 0.2µs 1001b = 51.2µs
0010b = 0.4µs 1010b = 102.4µs
0011b = 0.8µs 1011b = 102.4µs
0100b = 1.6µs 1100b = 102.4µs
0101b = 3.2µs 1101b = 102.4µs
0110b = 6.4µs 1110b = 102.4µs
0111b = 12.8µs 1111b = 102.4µs

5.1.2.30 FC_LF[5] Register (Offset = 65h) [Reset = X0h]

FC_LF[5] is shown in Table 7-69.

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Channel 5 UV and OV mapping to NRST error output

Table 7-69 FC_LF[5] Register Field Descriptions
BitFieldTypeResetDescription
7-5RESERVEDR0h Reserved
4OVHF_TO_NRSTR/W0h Maps MON5 OVHF fault to NRST
0 = Not mapped,
1 = Mapped
3UVHF_TO_NRSTR/WXh Maps MON5 UVHF fault to NRST
0 = Not mapped,
1 = Mapped
2-0RESERVEDR0h Reserved

5.1.2.31 UV_HF[6] Register (Offset = 70h) [Reset = X0h]

UV_HF[6] is shown in Table 7-70.

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Channel 6 High Frequency channel Under-Voltage threshold.

Table 7-70 UV_HF[6] Register Field Descriptions
BitFieldTypeResetDescription
7-0THRESHOLD[7:0]R/WXh Undervoltage threshold for High Frequency component of monitored channel.
The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT.
With scaling = 1x, the 8-bit value represents the range 0.2V to 1.475
V with 1 LSB = 5mV.
With scaling = 4x, the 8-bit value represents the range 0.8V to 5.9V with 1 LSB = 20mV.

5.1.2.32 OV_HF[6] Register (Offset = 71h) [Reset = X0h]

OV_HF[6] is shown in Table 7-71.

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Channel 6 High Frequency channel Over-Voltage threshold.

Table 7-71 OV_HF[6] Register Field Descriptions
BitFieldTypeResetDescription
7-0THRESHOLD[7:0]R/WXh Overvoltage threshold for High Frequency component of monitored channel.
The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT.
With scaling = 1x, the 8-bit value represents the range 0.2V to 1.475
V with 1 LSB = 5mV.
With scaling = 4x, the 8-bit value represents the range 0.8V to 5.9V with 1 LSB = 20mV.

5.1.2.33 FLT_HF[6] Register (Offset = 74h) [Reset = X0h]

FLT_HF[6] is shown in Table 7-72.

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Channel 6 UV and OV debouncing for High Frequency thresholds comparator output.

Table 7-72 FLT_HF[6] Register Field Descriptions
BitFieldTypeResetDescription
7-4OV_DEB[3:0]R/W0h Overvoltage comparator output debounce time (dont assert until output is stable for debounce time) for High Frequency monitoring path.
0000b = 0.1µs 1000b = 25.6µs
0001b = 0.2µs 1001b = 51.2µs
0010b = 0.4µs 1010b = 102.4µs
0011b = 0.8µs 1011b = 102.4µs
0100b = 1.6µs 1100b = 102.4µs
0101b = 3.2µs 1101b = 102.4µs
0110b = 6.4µs 1110b = 102.4µs
0111b = 12.8µs 1111b = 102.4µs
3-0UV_DEB[3:0]R/WXh Undervoltage comparator output debounce time (dont assert until output is stable for debounce time) for High Frequency monitoring path.
0000b = 0.1µs 1000b = 25.6µs
0001b = 0.2µs 1001b = 51.2µs
0010b = 0.4µs 1010b = 102.4µs
0011b = 0.8µs 1011b = 102.4µs
0100b = 1.6µs 1100b = 102.4µs
0101b = 3.2µs 1101b = 102.4µs
0110b = 6.4µs 1110b = 102.4µs
0111b = 12.8µs 1111b = 102.4µs

5.1.2.34 FC_LF[6] Register (Offset = 75h) [Reset = X0h]

FC_LF[6] is shown in Table 7-73.

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Channel 6 UV and OV mapping to NRST error output

Table 7-73 FC_LF[6] Register Field Descriptions
BitFieldTypeResetDescription
7-5RESERVEDR0h Reserved
4OVHF_TO_NRSTR/W0h Maps MON6 OVHF fault to NRST
0 = Not mapped,
1 = Mapped
3UVHF_TO_NRSTR/WXh Maps MON6 UVHF fault to NRST
0 = Not mapped,
1 = Mapped
2-0RESERVEDR0h Reserved

5.1.2.35 UV_HF[7] Register (Offset = 80h) [Reset = X0h]

UV_HF[7] is shown in Table 7-74.

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Channel 7 High Frequency channel Under-Voltage threshold.

Table 7-74 UV_HF[7] Register Field Descriptions
BitFieldTypeResetDescription
7-0THRESHOLD[7:0]R/WXh Undervoltage threshold for High Frequency component of monitored channel.
The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT.
With scaling = 1x, the 8-bit value represents the range 0.2V to 1.475
V with 1 LSB = 5mV.
With scaling = 4x, the 8-bit value represents the range 0.8V to 5.9V with 1 LSB = 20mV.

5.1.2.36 OV_HF[7] Register (Offset = 81h) [Reset = X0h]

OV_HF[7] is shown in Table 7-75.

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Channel 7 High Frequency channel Over-Voltage threshold.

Table 7-75 OV_HF[7] Register Field Descriptions
BitFieldTypeResetDescription
7-0THRESHOLD[7:0]R/WXh Overvoltage threshold for High Frequency component of monitored channel.
The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT.
With scaling = 1x, the 8-bit value represents the range 0.2V to 1.475
V with 1 LSB = 5mV.
With scaling = 4x, the 8-bit value represents the range 0.8V to 5.9V with 1 LSB = 20mV.

5.1.2.37 FLT_HF[7] Register (Offset = 84h) [Reset = X0h]

FLT_HF[7] is shown in Table 7-76.

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Channel 7 UV and OV debouncing for High Frequency thresholds comparator output.

Table 7-76 FLT_HF[7] Register Field Descriptions
BitFieldTypeResetDescription
7-4OV_DEB[3:0]R/W0h Overvoltage comparator output debounce time (dont assert until output is stable for debounce time) for High Frequency monitoring path.
0000b = 0.1µs 1000b = 25.6µs
0001b = 0.2µs 1001b = 51.2µs
0010b = 0.4µs 1010b = 102.4µs
0011b = 0.8µs 1011b = 102.4µs
0100b = 1.6µs 1100b = 102.4µs
0101b = 3.2µs 1101b = 102.4µs
0110b = 6.4µs 1110b = 102.4µs
0111b = 12.8µs 1111b = 102.4µs
3-0UV_DEB[3:0]R/WXh Undervoltage comparator output debounce time (dont assert until output is stable for debounce time) for High Frequency monitoring path.
0000b = 0.1µs 1000b = 25.6µs
0001b = 0.2µs 1001b = 51.2µs
0010b = 0.4µs 1010b = 102.4µs
0011b = 0.8µs 1011b = 102.4µs
0100b = 1.6µs 1100b = 102.4µs
0101b = 3.2µs 1101b = 102.4µs
0110b = 6.4µs 1110b = 102.4µs
0111b = 12.8µs 1111b = 102.4µs

5.1.2.38 FC_LF[7] Register (Offset = 85h) [Reset = X0h]

FC_LF[7] is shown in Table 7-77.

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Channel 7 UV and OV mapping to NRST error output

Table 7-77 FC_LF[7] Register Field Descriptions
BitFieldTypeResetDescription
7-5RESERVEDR0h Reserved
4OVHF_TO_NRSTR/W0h Maps MON7 OVHF fault to NRST
0 = Not mapped,
1 = Mapped
3UVHF_TO_NRSTR/WXh Maps MON7 UVHF fault to NRST
0 = Not mapped,
1 = Mapped
2-0RESERVEDR0h Reserved

5.1.2.39 UV_HF[8] Register (Offset = 90h) [Reset = X0h]

UV_HF[8] is shown in Table 7-78.

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Channel 8 High Frequency channel Under-Voltage threshold.

Table 7-78 UV_HF[8] Register Field Descriptions
BitFieldTypeResetDescription
7-0THRESHOLD[7:0]R/WXh Undervoltage threshold for High Frequency component of monitored channel.
The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT.
With scaling = 1x, the 8-bit value represents the range 0.2V to 1.475
V with 1 LSB = 5mV.
With scaling = 4x, the 8-bit value represents the range 0.8V to 5.9V with 1 LSB = 20mV.

5.1.2.40 OV_HF[8] Register (Offset = 91h) [Reset = X0h]

OV_HF[8] is shown in Table 7-79.

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Channel 8 High Frequency channel Over-Voltage threshold.

Table 7-79 OV_HF[8] Register Field Descriptions
BitFieldTypeResetDescription
7-0THRESHOLD[7:0]R/WXh Overvoltage threshold for High Frequency component of monitored channel.
The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT.
With scaling = 1x, the 8-bit value represents the range 0.2V to 1.475
V with 1 LSB = 5mV.
With scaling = 4x, the 8-bit value represents the range 0.8V to 5.9V with 1 LSB = 20mV.

5.1.2.41 FLT_HF[8] Register (Offset = 94h) [Reset = X0h]

FLT_HF[8] is shown in Table 7-80.

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Channel 8 UV and OV debouncing for High Frequency thresholds comparator output.

Table 7-80 FLT_HF[8] Register Field Descriptions
BitFieldTypeResetDescription
7-4OV_DEB[3:0]R/W0h Overvoltage comparator output debounce time (dont assert until output is stable for debounce time) for High Frequency monitoring path.
0000b = 0.1µs 1000b = 25.6µs
0001b = 0.2µs 1001b = 51.2µs
0010b = 0.4µs 1010b = 102.4µs
0011b = 0.8µs 1011b = 102.4µs
0100b = 1.6µs 1100b = 102.4µs
0101b = 3.2µs 1101b = 102.4µs
0110b = 6.4µs 1110b = 102.4µs
0111b = 12.8µs 1111b = 102.4µs
3-0UV_DEB[3:0]R/WXh Undervoltage comparator output debounce time (dont assert until output is stable for debounce time) for High Frequency monitoring path.
0000b = 0.1µs 1000b = 25.6µs
0001b = 0.2µs 1001b = 51.2µs
0010b = 0.4µs 1010b = 102.4µs
0011b = 0.8µs 1011b = 102.4µs
0100b = 1.6µs 1100b = 102.4µs
0101b = 3.2µs 1101b = 102.4µs
0110b = 6.4µs 1110b = 102.4µs
0111b = 12.8µs 1111b = 102.4µs

5.1.2.42 FC_LF[8] Register (Offset = 95h) [Reset = X0h]

FC_LF[8] is shown in Table 7-81.

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Channel 8 UV and OV mapping to NRST error output

Table 7-81 FC_LF[8] Register Field Descriptions
BitFieldTypeResetDescription
7-5RESERVEDR0h Reserved
4OVHF_TO_NRSTR/W0h Maps MON8 OVHF fault to NRST
0 = Not mapped,
1 = Mapped
3UVHF_TO_NRSTR/WXh Maps MON8 UVHF fault to NRST
0 = Not mapped,
1 = Mapped
2-0RESERVEDR0h Reserved

5.1.2.43 TI_CONTROL Register (Offset = 9Fh) [Reset = X0h]

TI_CONTROL is shown in Table 7-82.

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Manual BIST/Manual Reset via I2C/Reset delay

Table 7-82 TI_CONTROL Register Field Descriptions
BitFieldTypeResetDescription
7ENTER_BISTR/W0h Manual BIST.
1 = Enter BIST
6RESERVEDR0h Reserved
5I2C_MRR/W0h Manual Reset.
1 = Assert NRST low
4-3RESERVEDR0h Reserved
2-0RST_DLY[2:0]R/WXh Reset delay
000 = 200µs
001 = 1ms
010 = 10ms
011 = 16ms
100 = 20ms
101 = 70ms
110 = 100ms
111 = 200ms

5.1.2.44 AMSK_ON Register (Offset = A1h) [Reset = X0h]

AMSK_ON is shown in Table 7-83.

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Auto-mask UVHF and OVHF interrupts on power up transitions.

Table 7-83 AMSK_ON Register Field Descriptions
BitFieldTypeResetDescription
7MON[8]R/W0h Automask at power on for MON8.
0 = Disabled
1 = Enabled
6MON[7]R/W0h Automask at power on for MON7.
0 = Disabled
1 = Enabled
5MON[6]R/W0h Automask at power on for MON6.
0 = Disabled
1 = Enabled
4MON[5]R/W0h Automask at power on for MON5.
0 = Disabled
1 = Enabled
3MON[4]R/WXh Automask at power on for MON4.
0 = Disabled
1 = Enabled
2MON[3]R/WXh Automask at power on for MON3.
0 = Disabled
1 = Enabled
1MON[2]R/WXh Automask at power on for MON2.
0 = Disabled
1 = Enabled
1MON[1]R/WXh Automask at power on for MON1.
0 = Disabled
1 = Enabled
0RESERVEDR0h

5.1.2.45 AMSK_OFF Register (Offset = A2h) [Reset = X0h]

AMSK_OFF is shown in Table 7-84.

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Auto-mask UVHF and OVHF interrupts on power down transitions.

Table 7-84 AMSK_OFF Register Field Descriptions
BitFieldTypeResetDescription
7MON[8]R/W0h Automask at power off for MON8.
0 = Disabled
1 = Enabled
6MON[7]R/W0h Automask at power off for MON7.
0 = Disabled
1 = Enabled
5MON[6]R/W0h Automask at power off for MON6.
0 = Disabled
1 = Enabled
4MON[5]R/W0h Automask at power off for MON5.
0 = Disabled
1 = Enabled
3MON[4]R/WXh Automask at power off for MON4.
0 = Disabled
1 = Enabled
2MON[3]R/WXh Automask at power off for MON3.
0 = Disabled
1 = Enabled
1MON[2]R/WXh Automask at power off for MON2.
0 = Disabled
1 = Enabled
0MON[1]R/WXh Automask at power off for MON1.
0 = Disabled
1 = Enabled

5.1.2.46 AMSK_EXS Register (Offset = A3h) [Reset = X0h]

AMSK_EXS is shown in Table 7-85.

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Auto-mask UVHF and OVHF interrupts on exit sleep transitions.

Table 7-85 AMSK_EXS Register Field Descriptions
BitFieldTypeResetDescription
7MON[8]R/W0h Automask at exit sleep for MON8.
0 = Disabled
1 = Enabled
6MON[7]R/W0h Automask at exit sleep for MON7.
0 = Disabled
1 = Enabled
5MON[6]R/W0h Automask at exit sleep for MON6.
0 = Disabled
1 = Enabled
4MON[5]R/W0h Automask at exit sleep for MON5.
0 = Disabled
1 = Enabled
3MON[4]R/WXh Automask at exit sleep for MON4.
0 = Disabled
1 = Enabled
2MON[3]R/WXh Automask at exit sleep for MON3.
0 = Disabled
1 = Enabled
1MON[2]R/WXh Automask at exit sleep for MON2.
0 = Disabled
1 = Enabled
0MON[1]R/WXh Automask at exit sleep for MON1.
0 = Disabled
1 = Enabled

5.1.2.47 AMSK_ENS Register (Offset = A4h) [Reset = X0h]

AMSK_ENS is shown in Table 7-86.

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Auto-mask UVHF and OVHF interrupts on enter sleep transitions.

Table 7-86 AMSK_ENS Register Field Descriptions
BitFieldTypeResetDescription
7MON[8]R/W0h Automask at enter sleep for MON8.
0 = Disabled
1 = Enabled
6MON[7]R/W0h Automask at enter sleep for MON7.
0 = Disabled
1 = Enabled
5MON[6]R/W0h Automask at enter sleep for MON6.
0 = Disabled
1 = Enabled
4MON[5]R/W0h Automask at enter sleep for MON5.
0 = Disabled
1 = Enabled
3MON[4]R/WXh Automask at enter sleep for MON4.
0 = Disabled
1 = Enabled
2MON[3]R/WXh Automask at enter sleep for MON3.
0 = Disabled
1 = Enabled
1MON[2]R/WXh Automask at enter sleep for MON2.
0 = Disabled
1 = Enabled
0MON[1]R/WXh Automask at enter sleep for MON1.
0 = Disabled
1 = Enabled

5.1.2.48 BANK_SEL Register (Offset = F0h) [Reset = X0h]

BANK_SEL is shown in Table 7-87.

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Bank Select.

Table 7-87 BANK_SEL Register Field Descriptions
BitFieldTypeResetDescription
7-1RESERVEDR0h Reserved
0BANK_SelectR/WXh Represents bank selection.
0 = Bank 0
1 = Bank 1