The NRST pin features a programmable reset delay time that can be adjusted from 0.2ms to 200ms when using I2C RESET time delay register. NRST is an open-drain output, requires an external1kΩ to 100kΩ pullup resistor. When the device is powered up and POR is complete, NRST is asserted low until the BIST is complete. After the BIST, NRST remains high (not asserted) until triggered by a mappable fault condition. An NRST_MISMATCH fault asserts if the NRST pin is pulled to an unexpected state. For example, if the NRST pin is in a high-impedence state (logic high) and is externally pulled low, then an NRST_MISMATCH fault asserts. During an NRST toggle NRST mismatch is active after 2μs, NRST must exceed 0.6*VDD to be considered in a logic high state.

NRST is mappable to the OVHF and UVHF faults using the FC_LF[n] registers. If a monitored voltage falls or rises outside of the programmed OVHF and UVHF thresholds, then NRST is asserted, driving the NRST pin low. When the monitored voltage comes back into the valid window, a reset delay circuit is enabled that holds NRST low for a specified reset delay period (t_D).

The t_D period is determined by the RST_DLY[2:0] value found in the TI_CONTROL register. When the reset delay has elapsed, the NRST pin goes to a high-impedance state and uses a pullup resistor to hold NRST high. The pullup resistor must be connected to the proper voltage rail to allow other devices to be connected at the correct interface voltage. To maintain proper voltage levels, give consideration when choosing the pullup resistor values. The pullup resistor value is determined by output logic low voltage (VOL), capacitive loading, and leakage current.