SNVSCB5B March   2022  – May 2025 TPS388R0-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 I2C
      2. 7.3.2 Auto Mask (AMSK)
      3. 7.3.3 PEC
      4. 7.3.4 VDD
      5. 7.3.5 MON
      6. 7.3.6 NIRQ
      7. 7.3.7 NRST
    4. 7.4 Device Functional Modes
      1. 7.4.1 Built-In Self Test and Configuration Load
        1. 7.4.1.1 Notes on BIST Execution
      2. 7.4.2 TPS38800-Q1 Power ON
      3. 7.4.3 General Monitoring
        1. 7.4.3.1 IDLE Monitoring
        2. 7.4.3.2 ACTIVE Monitoring
        3. 7.4.3.3 Sequence Monitoring 1
          1. 7.4.3.3.1 ACT Transitions 0→1
          2. 7.4.3.3.2 SLEEP Transition 1→0
          3. 7.4.3.3.3 SLEEP Transition 0→1
        4. 7.4.3.4 Sequence Monitoring 2
          1. 7.4.3.4.1 ACT Transition 1→0
    5. 7.5 Register Maps
      1. 7.5.1 Registers Overview
        1. 7.5.1.1 BANK0 Registers
        2. 7.5.1.2 BANK1 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Multichannel Sequencer and Monitor
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
      4. 8.2.4 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Supply Guidelines
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Nomenclature
    2. 9.2 Documentation Support
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

7.5.1.1 BANK0 Registers

Table 7-4 lists the memory-mapped registers for the BANK0 registers. All register offset addresses not listed in Table 7-4 should be considered as reserved locations and the register contents should not be modified.

Table 7-4 BANK0 Registers
OffsetAcronymBit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
10hINT_SRCF_OTHERRESERVEDTESTCONTROLMONITOR
11hINT_MONITORRESERVEDOVHFRESERVEDUVHF
12hINT_UVHFF_UVHF[8]F_UVHF[7]F_UVHF[6]F_UVHF[5]F_UVHF[4]F_UVHF[3]F_UVHF[2]F_UVHF[1]
16hINT_OVHFF_OVHF[8]F_OVHF[7]F_OVHF[6]F_OVHF[5]F_OVHF[4]F_OVHF[3]F_OVHF[2]F_OVHF[1]
22hINT_CONTROLRESERVEDF_CRCF_NIRQF_TSDRESERVEDF_PEC
23hINT_TESTRESERVEDECC_SECECC_DEDBIST_Complete_INTBIST_Fail_INT
24hINT_VENDORSelf-Test_CRCLDO_OV_ErrorNRST_MISMATCHFreq_DEV_ErrorSHORT_DETOPEN_DETRESERVED
30hVMON_STATFAILSAFEST_BIST_CST_VDDST_NIRQRSVDACTIVERESERVED
31hTEST_INFORESERVEDECC_SECECC_DEDBIST_VMBIST_NVMBIST_LBIST_A
32hOFF_STATMON[8]MON[7]MON[6]MON[5]MON[4]MON[3]MON[2]MON[1]
90hSEQ_TIME_MSB[1]CLOCK[7:0]
91hSEQ_TIME_LSB[1]CLOCK[7:0]
92hSEQ_TIME_MSB[2]CLOCK[7:0]
93hSEQ_TIME_LSB[2]CLOCK[7:0]
94hSEQ_TIME_MSB[3]CLOCK[7:0]
95hSEQ_TIME_LSB[3]CLOCK[7:0]
96hSEQ_TIME_MSB[4]CLOCK[7:0]
97hSEQ_TIME_LSB[4]CLOCK[7:0]
98hSEQ_TIME_MSB[5]CLOCK[7:0]
99hSEQ_TIME_LSB[5]CLOCK[7:0]
9AhSEQ_TIME_MSB[6]CLOCK[7:0]
9BhSEQ_TIME_LSB[6]CLOCK[7:0]
9ChSEQ_TIME_MSB[7]CLOCK[7:0]
9DhSEQ_TIME_LSB[7]CLOCK[7:0]
9EhSEQ_TIME_MSB[8]CLOCK[7:0]
9FhSEQ_TIME_LSB[8]CLOCK[7:0]
F0hBANK_SELRESERVEDBANK_Select
F1hPROT1RESERVEDWRKCRESERVEDCFGIENMONRESERVED
F2hPROT2RESERVEDWRKCRESERVEDCFGIENMONRESERVED
F3hPROT_MONMON[8]MON[7]MON[6]MON[5]MON[4]MON[3]MON[2]MON[1]
F9hI2CADDRRESERVEDADDR_NVM[3:0]ADDR_STRAP[2:0]
FAhDEV_CFGRESERVEDRESERVED

Complex bit access types are encoded to fit into small table cells. Table 7-5 shows the codes that are used for access types in this section.

Table 7-5 BANK0 Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
W1CW
1C		Write
1 to clear
Reset or Default Value
-nValue after reset or the default value

5.1.1.1 INT_SRC Register (Offset = 10h) [Reset = X0h]

INT_SRC is shown in Table 7-6.

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Global Interrupt Source Status register.

Table 7-6 INT_SRC Register Field Descriptions
BitFieldTypeResetDescription
7F_OTHERR0h Vendor internal defined faults. Details reported in INT_Vendor. Represents ORed value of all bits in INT_Vendor.
0 = No Vendor defined faults detected
1 = Vendor defined faults detected
6-3RESERVEDR0h Reserved
2TESTRXh Internal test or configuration load fault. Details reported in INT_TEST. Represents ORed value of all bits in INT_TEST.
0 = No test/configuration fault detected
1 = Test/configuration fault detected
1CONTROLRXh Control status or communication fault. Details reported in INT_CONTROL. Represents ORed value of all bits in INT_CONTROL.
0 = No status or communication fault detected
1 = Status or communication fault detected
0MONITORRXh Voltage monitor fault. Details reported in INT_MONITOR. Represents ORed value of all bits in INT_MONITOR.
0 = No voltage fault detected
1 = Voltage fault detected

5.1.1.2 INT_MONITOR Register (Offset = 11h) [Reset = X0h]

INT_MONITOR is shown in Table 7-7.

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Voltage Monitor Interrupt Status register.

Table 7-7 INT_MONITOR Register Field Descriptions
BitFieldTypeResetDescription
7-3RESERVEDR0h Reserved
2OVHFRXh Over-Voltage High Frequency Fault reported by comparator based monitoring. Details reported in INT_OVHF. Represents ORed value of all bits in INT_OVHF.
0 = No OVHF fault detected
1 = OVHF fault detected
1RESERVEDR0h Reserved
0UVHFRXh Under-Voltage High Frequency Fault reported by comparator based monitoring. Details reported in INT_UVHF. Represents ORed value of all bits in INT_UVHF.
0 = No UVHF fault detected
1 = UVHF fault detected

5.1.1.3 INT_UVHF Register (Offset = 12h) [Reset = X0h]

INT_UVHF is shown in Table 7-8.

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High Frequency channel Under-Voltage Interrupt Status register.

Table 7-8 INT_UVHF Register Field Descriptions
BitFieldTypeResetDescription
7F_UVHF[8]R/W1C0h Under-Voltage High Frequency Fault for MON8. Trips if MON8 High Frequency signal goes below UVHF[8].
0 = MON8 has no UVHF fault detected (or interrupt disabled in IEN_UVHF register)
1 = MON8 has UVHF fault detected
The recovery of the fault condition does NOT clear the bit. The fault is only cleared when the host performs a write-1-to-clear. Write-1-to-clear clears the bit only if the UVHF fault condition is also removed (MON8 High Frequency signal is above UVHF[8]).
6F_UVHF[7]R/W1C0h Under-Voltage High Frequency Fault for MON7. Trips if MON7 High Frequency signal goes below UVHF[7].
0 = MON7 has no UVHF fault detected (or interrupt disabled in IEN_UVHF register)
1 = MON7 has UVHF fault detected
The recovery of the fault condition does NOT clear the bit. The fault is only cleared when the host performs a write-1-to-clear. Write-1-to-clear clears the bit only if the UVHF fault condition is also removed (MON7 High Frequency signal is above UVHF[7]).
5F_UVHF[6]R/W1C0h Under-Voltage High Frequency Fault for MON6. Trips if MON6 High Frequency signal goes below UVHF[6].
0 = MON6 has no UVHF fault detected (or interrupt disabled in IEN_UVHF register)
1 = MON6 has UVHF fault detected
The recovery of the fault condition does NOT clear the bit. The fault is only cleared when the host performs a write-1-to-clear. Write-1-to-clear clears the bit only if the UVHF fault condition is also removed (MON6 High Frequency signal is above UVHF[6]).
4F_UVHF[5]R/W1C0h Under-Voltage High Frequency Fault for MON5. Trips if MON5 High Frequency signal goes below UVHF[5].
0 = MON5 has no UVHF fault detected (or interrupt disabled in IEN_UVHF register)
1 = MON5 has UVHF fault detected
The recovery of the fault condition does NOT clear the bit. The fault is only cleared when the host performs a write-1-to-clear. Write-1-to-clear clears the bit only if the UVHF fault condition is also removed (MON5 High Frequency signal is above UVHF[5]).
3F_UVHF[4]R/W1CXh Under-Voltage High Frequency Fault for MON4. Trips if MON4 High Frequency signal goes below UVHF[4].
0 = MON4 has no UVHF fault detected (or interrupt disabled in IEN_UVHF register)
1 = MON4 has UVHF fault detected
The recovery of the fault condition does NOT clear the bit. The fault is only cleared when the host performs a write-1-to-clear. Write-1-to-clear clears the bit only if the UVHF fault condition is also removed (MON4 High Frequency signal is above UVHF[4]).
2F_UVHF[3]R/W1CXh Under-Voltage High Frequency Fault for MON3. Trips if MON3 High Frequency signal goes below UVHF[3].
0 = MON3 has no UVHF fault detected (or interrupt disabled in IEN_UVHF register)
1 = MON3 has UVHF fault detected
The recovery of the fault condition does NOT clear the bit. The fault is only cleared when the host performs a write-1-to-clear. Write-1-to-clear clears the bit only if the UVHF fault condition is also removed (MON3 High Frequency signal is above UVHF[3]).
1F_UVHF[2]R/W1CXh Under-Voltage High Frequency Fault for MON2. Trips if MON2 High Frequency signal goes below UVHF[2].
0 = MON2 has no UVHF fault detected (or interrupt disabled in IEN_UVHF register)
1 = MON2 has UVHF fault detected
The recovery of the fault condition does NOT clear the bit. The fault is only cleared when the host performs a write-1-to-clear. Write-1-to-clear clears the bit only if the UVHF fault condition is also removed (MON2 High Frequency signal is above UVHF[2]).
0F_UVHF[1]R/W1CXh Under-Voltage High Frequency Fault for MON1. Trips if MON1 High Frequency signal goes below UVHF[1].
0 = MON1 has no UVHF fault detected (or interrupt disabled in IEN_UVHF register)
1 = MON1 has UVHF fault detected
The recovery of the fault condition does NOT clear the bit. The fault is only cleared when the host performs a write-1-to-clear. Write-1-to-clear clears the bit only if the UVHF fault condition is also removed (MON1 High Frequency signal is above UVHF[1]).

5.1.1.4 INT_OVHF Register (Offset = 16h) [Reset = X0h]

INT_OVHF is shown in Table 7-9.

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High Frequency channel Over-Voltage Interrupt Status register

Table 7-9 INT_OVHF Register Field Descriptions
BitFieldTypeResetDescription
7F_OVHF[8]R/W1C0h Over-Voltage High Frequency Fault for MON8. Trips if MON8 High Frequency signal goes above OVHF[8].
0 = MON8 has noOVHF fault detected (or interrupt disabled in IEN_OVHF register)
1 = MON8 has OVHF fault detected
The recovery of the fault condition does NOT clear the bit. The fault is only cleared when the host performs a write-1-to-clear. Write-1-to-clear clears the bit only if the OVHF fault condition is also removed (MON8 High Frequency signal is below OVHF[8])
6F_OVHF[7]R/W1C0h Over-Voltage High Frequency Fault for MON7. Trips if MON7 High Frequency signal goes above OVHF[7].
0 = MON7 has noOVHF fault detected (or interrupt disabled in IEN_OVHF register)
1 = MON7 has OVHF fault detected
The recovery of the fault condition does NOT clear the bit. The fault is only cleared when the host performs a write-1-to-clear. Write-1-to-clear clears the bit only if the OVHF fault condition is also removed (MON7 High Frequency signal is below OVHF[7])
5F_OVHF[6]R/W1C0h Over-Voltage High Frequency Fault for MON6. Trips if MON6 High Frequency signal goes above OVHF[6].
0 = MON6 has noOVHF fault detected (or interrupt disabled in IEN_OVHF register)
1 = MON6 has OVHF fault detected
The recovery of the fault condition does NOT clear the bit. The fault is only cleared when the host performs a write-1-to-clear. Write-1-to-clear clears the bit only if the OVHF fault condition is also removed (MON6 High Frequency signal is below OVHF[6])
4F_OVHF[5]R/W1C0h Over-Voltage High Frequency Fault for MON5. Trips if MON5 High Frequency signal goes above OVHF[5].
0 = MON5 has noOVHF fault detected (or interrupt disabled in IEN_OVHF register)
1 = MON5 has OVHF fault detected
The recovery of the fault condition does NOT clear the bit. The fault is only cleared when the host performs a write-1-to-clear. Write-1-to-clear clears the bit only if the OVHF fault condition is also removed (MON5 High Frequency signal is below OVHF[5])
3F_OVHF[4]R/W1CXh Over-Voltage High Frequency Fault for MON4. Trips if MON4 High Frequency signal goes above OVHF[4].
0 = MON4 has noOVHF fault detected (or interrupt disabled in IEN_OVHF register)
1 = MON4 has OVHF fault detected
The recovery of the fault condition does NOT clear the bit. The fault is only cleared when the host performs a write-1-to-clear. Write-1-to-clear clears the bit only if the OVHF fault condition is also removed (MON4 High Frequency signal is below OVHF[4])
2F_OVHF[3]R/W1CXh Over-Voltage High Frequency Fault for MON3. Trips if MON3 High Frequency signal goes above OVHF[3].
0 = MON3 has no OVHF fault detected (or interrupt disabled in IEN_OVHF register)
1 = MON3 has OVHF fault detected
The recovery of the fault condition does NOT clear the bit. The fault is only cleared when the host performs a write-1-to-clear. Write-1-to-clear clears the bit only if the OVHF fault condition is also removed (MON3 High Frequency signal is below OVHF[3])
1F_OVHF[2]R/W1CXh Over-Voltage High Frequency Fault for MON2. Trips if MON2 High Frequency signal goes above OVHF[2].
0 = MON2 has no OVHF fault detected (or interrupt disabled in IEN_OVHF register)
1 = MON2 has OVHF fault detected
The recovery of the fault condition does NOT clear the bit. The fault is only cleared when the host performs a write-1-to-clear. Write-1-to-clear clears the bit only if the OVHF fault condition is also removed (MON2 High Frequency signal is below OVHF[2])
0F_OVHF[1]R/W1CXh Over-Voltage High Frequency Fault for MON1. Trips if MON1 High Frequency signal goes above OVHF[1].
0 = MON1 has no OVHF fault detected (or interrupt disabled in IEN_OVHF register)
1 = MON1 has OVHF fault detected
The recovery of the fault condition does NOT clear the bit. The fault is only cleared when the host performs a write-1-to-clear. Write-1-to-clear clears the bit only if the OVHF fault condition is also removed (MON1 High Frequency signal is below OVHF[1])

5.1.1.5 INT_CONTROL Register (Offset = 22h) [Reset = X0h]

INT_CONTROL is shown in Table 7-10.

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Control and Communication Interrupt Status register.

Table 7-10 INT_CONTROL Register Field Descriptions
BitFieldTypeResetDescription
7-5RESERVEDR0h Reserved
4F_CRCR/W1C0h Runtime register CRC Fault:
0 = No fault detected (or IEN_CONTROL.RT_CRC is disabled)
1 = Register CRC fault detected
The recovery of the fault condition does NOT clear the bit. The fault is only cleared when the host performs a write-1-to-clear. Write-1-to-clear clears the bit. The bit is set again during next register CRC check if the same fault is detected
3F_NIRQR/W1CXh Interrupt pin fault (fault bit always enabled; no enable bit available):
0 = No fault detected on NIRQ pin
1 = Low resistance path to supply detected on NIRQ pin
The recovery of the fault condition does NOT clear the bit. The fault is only cleared when the host performs a write-1-to-clear. Write-1-to-clear clears the bit only if the NIRQ fault condition is also removed.
2F_TSDR/W1CXh Thermal Shutdown fault:
0 = No TSD fault detected (or IEN_CONTROL.TSD is disabled)
1 = TSD fault detected
The recovery of the fault condition does NOT clear the bit. The fault is only cleared when the host performs a write-1-to-clear. Write-1-to-clear clears the bit only if the TSD fault condition is also removed
1RESERVEDR0h Reserved
0F_PECR/W1CXh Packet Error Checking fault:
0 = PEC mismatch has not occurred (or IEN_CONTROL.PEC is disabled)
1 = PEC mismatch has occurred, or VMON_MISC.REQ_PEC=1 and PEC is missing in a write transaction
The recovery of the fault condition does NOT clear the bit. The fault is only cleared when the host performs a write-1-to-clear. Write-1-to-clear clears the bit. The bit is set again during next I2C transaction if the same fault is detected.

5.1.1.6 INT_TEST Register (Offset = 23h) [Reset = X0h]

INT_TEST is shown in Table 7-11.

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Internal Test and Configuration Load Interrupt Status register.

Table 7-11 INT_TEST Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR0h Reserved
3ECC_SECR/W1CXh ECC single-error corrected on OTP configuration load:
0 = No single-error corrected (or IEN_TEST.ECC_SEC is disabled)
1 = Single-error corrected
Write-1-to-clear clears the bit. The bit is set again during next OTP configuration load if the same fault is detected.
2ECC_DEDR/W1CXh ECC double-error detected on OTP configuration load:
0 = No double-error detected on OTP load
1 = Double-error detected on OTP load
The fault bit is always enabled (there is no associated interrupt enable bit). The device is moved to a failsafe mode on double error detection.
1BIST_Complete_INTR/W1CXh Indication of Built-In Self-Test complete:
0 = BIST not complete (or IEN_TEST.BIST_C is disabled)
1 = BIST complete
Write-1-to-clear clears the bit. The bit is set again on completion of next BIST execution
0BIST_Fail_INTR/W1CXh Built-In Self-Test fault:
0 = No BIST fault detected (or IEN_TEST.BIST is disabled)
1 = BIST fault detected
Write-1-to-clear clears the bit. The bit is set again during next BIST execution if the fault is detected

5.1.1.7 INT_VENDOR Register (Offset = 24h) [Reset = X0h]

INT_VENDOR is shown in Table 7-12.

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Vendor Specific Internal Interrupt Status register.

Table 7-12 INT_VENDOR Register Field Descriptions
BitFieldTypeResetDescription
7Self-Test_CRCR/W1C0h Startup register CRC self-test
0 = Self-test Pass
1 = Self-test Fail
Write-1-to clear
6LDO_OV_ErrorR/W1C0h Internal LDO Overvoltage error.
0 = No internal LDO overvoltage fault detected
1 = Internal LDO overvoltage fault detected
The recovery of the fault condition does NOT clear the bit. The fault is only cleared when the host performs a write-1-to-clear. Write-1-to-clear clears the bit only if the LDO fault condition is also removed.
5NRST_MISMATCHR/W1C0h Designates error due to drive state and read back. During an NRST toggle NRST mismatch is active after 2µs, NRST must exceed 0.6*VDD to be considered in a logic high state.
0 = No fault detected on NRST pin
1 = Error due to drive state and read back.
The recovery of the fault condition does NOT clear the bit. The fault is only cleared when the host performs a write-1-to-clear. Write-1-to-clear clears the bit only if the NRST fault condition is also removed.
4Freq_DEV_ErrorR/W1C0h Designates internal frequency errors.
0 = No internal frequency fault detected
1 = Internal frequency fault detected
The recovery of the fault condition does NOT clear the bit. The fault is only cleared when the host performs a write-1-to-clear. Write-1-to-clear clears the bit only if the frequency fault condition is also removed.
3SHORT_DETR/W1CXh Address pin short detect.
0 = No internal address pin short fault detected
1 = Internal address pin short fault detected
The recovery of the fault condition does NOT clear the bit. The fault is only cleared when the host performs a write-1-to-clear. Write-1-to-clear clears the bit only if the internal address pin short fault condition is also removed.
2OPEN_DETR/W1CXh Address pin open detect.
0 = No internal address pin open fault detected
1 = Internal address pin open fault detected
The recovery of the fault condition does NOT clear the bit. The fault is only cleared when the host performs a write-1-to-clear. Write-1-to-clear clears the bit only if the internal address pin open fault condition is also removed.
1-0RESERVEDR0h Reserved

5.1.1.8 VMON_STAT Register (Offset = 30h) [Reset = X0h]

VMON_STAT is shown in Table 7-13.

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Status flags for internal operations and other non critical conditions.

Table 7-13 VMON_STAT Register Field Descriptions
BitFieldTypeResetDescription
7FAILSAFER0h 1 = Device in FAILSAFE state
6ST_BIST_CR0h Built-In Self-Test state:
0 = BIST not complete
1 = BIST complete
5ST_VDDR0h Status VDD
4ST_NIRQR0h Status NIRQ pin
3RSVDRXh RSVD
2ACTIVERXh 1 = Device in ACTIVE state
1-0RESERVEDR0h Reserved

5.1.1.9 TEST_INFO Register (Offset = 31h) [Reset = X0h]

TEST_INFO is shown in Table 7-14.

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Internal Self-Test and ECC information.

Table 7-14 TEST_INFO Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR0h Reserved
5ECC_SECR0h Status of ECC single-error correction on OTP configuration load.
0 = no error correction applied
1 = single-error correction applied
4ECC_DEDR0h Status of ECC double-error detection on OTP configuration load.
0 = no double-error detected
1 = double-error detected
3BIST_VMRXh Status of Volatile Memory test output from BIST.
0 = Volatile Memory test pass
1 = Volatile Memory test fail
2BIST_NVMRXh Status of Non-Volatile Memory test output from BIST.
0 = Non-Volatile Memory test pass
1 = Non-Volatile Memory test fail
1BIST_LRXh Status of Logic test output from BIST.
0 = Logic test pass
1 = Logic test fail
0BIST_ARXh Status of Analog test output from BIST.
0 = Analog test pass
1 = Analog test fail

5.1.1.10 OFF_STAT Register (Offset = 32h) [Reset = X0h]

OFF_STAT is shown in Table 7-15.

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Channel OFF status.

Table 7-15 OFF_STAT Register Field Descriptions
BitFieldTypeResetDescription
7MON[8]R0h Represents the OFF status of each channel:
0 = channel 8 is NOT OFF
1 = channel 8 is OFF (below OFF threshold)
6MON[7]R0h Represents the OFF status of each channel:
0 = channel 7 is NOT OFF
1 = channel 7 is OFF (below OFF threshold)
5MON[6]R0h Represents the OFF status of each channel:
0 = channel 6 is NOT OFF
1 = channel 6 is OFF (below OFF threshold)
4MON[5]R0h Represents the OFF status of each channel:
0 = channel 5 is NOT OFF
1 = channel 5 is OFF (below OFF threshold)
3MON[4]RXh Represents the OFF status of each channel:
0 = channel 4 is NOT OFF
1 = channel 4 is OFF (below OFF threshold)
2MON[3]RXh Represents the OFF status of each channel:
0 = channel 3 is NOT OFF
1 = channel 3 is OFF (below OFF threshold)
1MON[2]RXh Represents the OFF status of each channel:
0 = channel 2 is NOT OFF
1 = channel 2 is OFF (below OFF threshold)
0MON[1]RXh Represents the OFF status of each channel:
0 = channel 1 is NOT OFF
1 = channel 1 is OFF (below OFF threshold)

5.1.1.11 SEQ_TIME_MSB[1] Register (Offset = 90h) [Reset = X0h]

SEQ_TIME_MSB[1] is shown in Table 7-16.

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Channel N Sequence timestamp value MSB and LSB (all sequences).

Table 7-16 SEQ_TIME_MSB[1] Register Field Descriptions
BitFieldTypeResetDescription
7-0CLOCK[7:0]RXh This register stores the MSB of the sequence timestamp for channel 1. The sequence timer value is the time assigned to the channel during the sequence triggered by ACT or SLEEP. The timestamp is stored when the voltage rising level passes the UV_LF[1] threshold for Power ON and Sleep Exit sequences (ACT 01 or SLEEP 01). The timestamp is stored when the voltage falling level passes the OFF threshold (200mV) for Power OFF and Sleep Entry sequences (ACT 10 or SLEEP 10). The least significant bit corresponds to 50µs (equal to tSEQ_LSB).

5.1.1.12 SEQ_TIME_LSB[1] Register (Offset = 91h) [Reset = X0h]

SEQ_TIME_LSB[1] is shown in Table 7-17.

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Channel N Sequence timestamp value MSB and LSB (all sequences).

Table 7-17 SEQ_TIME_LSB[1] Register Field Descriptions
BitFieldTypeResetDescription
7-0CLOCK[7:0]RXh This register stores the LSB of the sequence timestamp for channel 1. The sequence timer value is the time assigned to the channel during the sequence triggered by ACT or SLEEP. The timestamp is stored when the voltage rising level passes the UV_LF[1] threshold for Power ON and Sleep Exit sequences (ACT 01 or SLEEP 01). The timestamp is stored when the voltage falling level passes the OFF threshold (200mV) for Power OFF and Sleep Entry sequences (ACT 10 or SLEEP 10). The least significant bit corresponds to 50µs (equal to tSEQ_LSB).

5.1.1.13 SEQ_TIME_MSB[2] Register (Offset = 92h) [Reset = X0h]

SEQ_TIME_MSB[2] is shown in Table 7-18.

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Channel N Sequence timestamp value MSB and LSB (all sequences).

Table 7-18 SEQ_TIME_MSB[2] Register Field Descriptions
BitFieldTypeResetDescription
7-0CLOCK[7:0]RXh This register stores the MSB of the sequence timestamp for channel 2. The sequence timer value is the time assigned to the channel during the sequence triggered by ACT or SLEEP. The timestamp is stored when the voltage rising level passes the UV_LF[2] threshold for Power ON and Sleep Exit sequences (ACT 01 or SLEEP 01). The timestamp is stored when the voltage falling level passes the OFF threshold (200mV) for Power OFF and Sleep Entry sequences (ACT 10 or SLEEP 10). The least significant bit corresponds to 50µs (equal to tSEQ_LSB).

5.1.1.14 SEQ_TIME_LSB[2] Register (Offset = 93h) [Reset = X0h]

SEQ_TIME_LSB[2] is shown in Table 7-19.

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Channel N Sequence timestamp value MSB and LSB (all sequences).

Table 7-19 SEQ_TIME_LSB[2] Register Field Descriptions
BitFieldTypeResetDescription
7-0CLOCK[7:0]RXh This register stores the LSB of the sequence timestamp for channel 2. The sequence timer value is the time assigned to the channel during the sequence triggered by ACT or SLEEP. The timestamp is stored when the voltage rising level passes the UV_LF[2] threshold for Power ON and Sleep Exit sequences (ACT 01 or SLEEP 01). The timestamp is stored when the voltage falling level passes the OFF threshold (200mV) for Power OFF and Sleep Entry sequences (ACT 10 or SLEEP 10). The least significant bit corresponds to 50µs (equal to tSEQ_LSB).

5.1.1.15 SEQ_TIME_MSB[3] Register (Offset = 94h) [Reset = X0h]

SEQ_TIME_MSB[3] is shown in Table 7-20.

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Channel N Sequence timestamp value MSB and LSB (all sequences).

Table 7-20 SEQ_TIME_MSB[3] Register Field Descriptions
BitFieldTypeResetDescription
7-0CLOCK[7:0]RXh This register stores the MSB of the sequence timestamp for channel 3. The sequence timer value is the time assigned to the channel during the sequence triggered by ACT or SLEEP. The timestamp is stored when the voltage rising level passes the UV_LF[3] threshold for Power ON and Sleep Exit sequences (ACT 01 or SLEEP 01). The timestamp is stored when the voltage falling level passes the OFF threshold (200mV) for Power OFF and Sleep Entry sequences (ACT 10 or SLEEP 10). The least significant bit corresponds to 50µs (equal to tSEQ_LSB).

5.1.1.16 SEQ_TIME_LSB[3] Register (Offset = 95h) [Reset = X0h]

SEQ_TIME_LSB[3] is shown in Table 7-21.

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Channel N Sequence timestamp value MSB and LSB (all sequences).

Table 7-21 SEQ_TIME_LSB[3] Register Field Descriptions
BitFieldTypeResetDescription
7-0CLOCK[7:0]RXh This register stores the LSB of the sequence timestamp for channel 3. The sequence timer value is the time assigned to the channel during the sequence triggered by ACT or SLEEP. The timestamp is stored when the voltage rising level passes the UV_LF[3] threshold for Power ON and Sleep Exit sequences (ACT 01 or SLEEP 01). The timestamp is stored when the voltage falling level passes the OFF threshold (200mV) for Power OFF and Sleep Entry sequences (ACT 10 or SLEEP 10). The least significant bit corresponds to 50µs (equal to tSEQ_LSB).

5.1.1.17 SEQ_TIME_MSB[4] Register (Offset = 96h) [Reset = X0h]

SEQ_TIME_MSB[4] is shown in Table 7-22.

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Channel N Sequence timestamp value MSB and LSB (all sequences).

Table 7-22 SEQ_TIME_MSB[4] Register Field Descriptions
BitFieldTypeResetDescription
7-0CLOCK[7:0]RXh This register stores the MSB of the sequence timestamp for channel 4. The sequence timer value is the time assigned to the channel during the sequence triggered by ACT or SLEEP. The timestamp is stored when the voltage rising level passes the UV_LF[4] threshold for Power ON and Sleep Exit sequences (ACT 01 or SLEEP 01). The timestamp is stored when the voltage falling level passes the OFF threshold (200mV) for Power OFF and Sleep Entry sequences (ACT 10 or SLEEP 10). The least significant bit corresponds to 50µs (equal to tSEQ_LSB).

5.1.1.18 SEQ_TIME_LSB[4] Register (Offset = 97h) [Reset = X0h]

SEQ_TIME_LSB[4] is shown in Table 7-23.

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Channel N Sequence timestamp value MSB and LSB (all sequences).

Table 7-23 SEQ_TIME_LSB[4] Register Field Descriptions
BitFieldTypeResetDescription
7-0CLOCK[7:0]RXh This register stores the LSB of the sequence timestamp for channel 4. The sequence timer value is the time assigned to the channel during the sequence triggered by ACT or SLEEP. The timestamp is stored when the voltage rising level passes the UV_LF[4] threshold for Power ON and Sleep Exit sequences (ACT 01 or SLEEP 01). The timestamp is stored when the voltage falling level passes the OFF threshold (200mV) for Power OFF and Sleep Entry sequences (ACT 10 or SLEEP 10). The least significant bit corresponds to 50µs (equal to tSEQ_LSB).

5.1.1.19 SEQ_TIME_MSB[5] Register (Offset = 98h) [Reset = X0h]

SEQ_TIME_MSB[5] is shown in Table 7-24.

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Channel N Sequence timestamp value MSB and LSB (all sequences).

Table 7-24 SEQ_TIME_MSB[5] Register Field Descriptions
BitFieldTypeResetDescription
7-0CLOCK[7:0]RXh This register stores the MSB of the sequence timestamp for channel 5. The sequence timer value is the time assigned to the channel during the sequence triggered by ACT or SLEEP. The timestamp is stored when the voltage rising level passes the UV_LF[5] threshold for Power ON and Sleep Exit sequences (ACT 01 or SLEEP 01). The timestamp is stored when the voltage falling level passes the OFF threshold (200mV) for Power OFF and Sleep Entry sequences (ACT 10 or SLEEP 10). The least significant bit corresponds to 50µs (equal to tSEQ_LSB).

5.1.1.20 SEQ_TIME_LSB[5] Register (Offset = 99h) [Reset = X0h]

SEQ_TIME_LSB[5] is shown in Table 7-25.

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Channel N Sequence timestamp value MSB and LSB (all sequences).

Table 7-25 SEQ_TIME_LSB[5] Register Field Descriptions
BitFieldTypeResetDescription
7-0CLOCK[7:0]RXh This register stores the LSB of the sequence timestamp for channel 5. The sequence timer value is the time assigned to the channel during the sequence triggered by ACT or SLEEP. The timestamp is stored when the voltage rising level passes the UV_LF[5] threshold for Power ON and Sleep Exit sequences (ACT 01 or SLEEP 01). The timestamp is stored when the voltage falling level passes the OFF threshold (200mV) for Power OFF and Sleep Entry sequences (ACT 10 or SLEEP 10). The least significant bit corresponds to 50µs (equal to tSEQ_LSB).

5.1.1.21 SEQ_TIME_MSB[6] Register (Offset = 9Ah) [Reset = X0h]

SEQ_TIME_MSB[6] is shown in Table 7-26.

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Channel N Sequence timestamp value MSB and LSB (all sequences).

Table 7-26 SEQ_TIME_MSB[6] Register Field Descriptions
BitFieldTypeResetDescription
7-0CLOCK[7:0]RXh This register stores the MSB of the sequence timestamp for channel 6. The sequence timer value is the time assigned to the channel during the sequence triggered by ACT or SLEEP. The timestamp is stored when the voltage rising level passes the UV_LF[6] threshold for Power ON and Sleep Exit sequences (ACT 01 or SLEEP 01). The timestamp is stored when the voltage falling level passes the OFF threshold (200mV) for Power OFF and Sleep Entry sequences (ACT 10 or SLEEP 10). The least significant bit corresponds to 50µs (equal to tSEQ_LSB).

5.1.1.22 SEQ_TIME_LSB[6] Register (Offset = 9Bh) [Reset = X0h]

SEQ_TIME_LSB[6] is shown in Table 7-27.

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Channel N Sequence timestamp value MSB and LSB (all sequences).

Table 7-27 SEQ_TIME_LSB[6] Register Field Descriptions
BitFieldTypeResetDescription
7-0CLOCK[7:0]RXh This register stores the LSB of the sequence timestamp for channel 6. The sequence timer value is the time assigned to the channel during the sequence triggered by ACT or SLEEP. The timestamp is stored when the voltage rising level passes the UV_LF[6] threshold for Power ON and Sleep Exit sequences (ACT 01 or SLEEP 01). The timestamp is stored when the voltage falling level passes the OFF threshold (200mV) for Power OFF and Sleep Entry sequences (ACT 10 or SLEEP 10). The least significant bit corresponds to 50µs (equal to tSEQ_LSB).

5.1.1.23 SEQ_TIME_MSB[7] Register (Offset = 9Ch) [Reset = X0h]

SEQ_TIME_MSB[7] is shown in Table 7-28.

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Channel N Sequence timestamp value MSB and LSB (all sequences).

Table 7-28 SEQ_TIME_MSB[7] Register Field Descriptions
BitFieldTypeResetDescription
7-0CLOCK[7:0]RXh This register stores the MSB of the sequence timestamp for channel 7. The sequence timer value is the time assigned to the channel during the sequence triggered by ACT or SLEEP. The timestamp is stored when the voltage rising level passes the UV_LF[7] threshold for Power ON and Sleep Exit sequences (ACT 01 or SLEEP 01). The timestamp is stored when the voltage falling level passes the OFF threshold (200mV) for Power OFF and Sleep Entry sequences (ACT 10 or SLEEP 10). The least significant bit corresponds to 50µs (equal to tSEQ_LSB).

5.1.1.24 SEQ_TIME_LSB[7] Register (Offset = 9Dh) [Reset = X0h]

SEQ_TIME_LSB[7] is shown in Table 7-29.

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Channel N Sequence timestamp value MSB and LSB (all sequences).

Table 7-29 SEQ_TIME_LSB[7] Register Field Descriptions
BitFieldTypeResetDescription
7-0CLOCK[7:0]RXh This register stores the LSB of the sequence timestamp for channel 7. The sequence timer value is the time assigned to the channel during the sequence triggered by ACT or SLEEP. The timestamp is stored when the voltage rising level passes the UV_LF[7] threshold for Power ON and Sleep Exit sequences (ACT 01 or SLEEP 01). The timestamp is stored when the voltage falling level passes the OFF threshold (200mV) for Power OFF and Sleep Entry sequences (ACT 10 or SLEEP 10). The least significant bit corresponds to 50µs (equal to tSEQ_LSB).

5.1.1.25 SEQ_TIME_MSB[8] Register (Offset = 9Eh) [Reset = X0h]

SEQ_TIME_MSB[8] is shown in Table 7-30.

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Channel N Sequence timestamp value MSB and LSB (all sequences).

Table 7-30 SEQ_TIME_MSB[8] Register Field Descriptions
BitFieldTypeResetDescription
7-0CLOCK[7:0]RXh This register stores the MSB of the sequence timestamp for channel 8. The sequence timer value is the time assigned to the channel during the sequence triggered by ACT or SLEEP. The timestamp is stored when the voltage rising level passes the UV_LF[8] threshold for Power ON and Sleep Exit sequences (ACT 01 or SLEEP 01). The timestamp is stored when the voltage falling level passes the OFF threshold (200mV) for Power OFF and Sleep Entry sequences (ACT 10 or SLEEP 10). The least significant bit corresponds to 50µs (equal to tSEQ_LSB).

5.1.1.26 SEQ_TIME_LSB[8] Register (Offset = 9Fh) [Reset = X0h]

SEQ_TIME_LSB[8] is shown in Table 7-31.

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Channel N Sequence timestamp value MSB and LSB (all sequences).

Table 7-31 SEQ_TIME_LSB[8] Register Field Descriptions
BitFieldTypeResetDescription
7-0CLOCK[7:0]RXh This register stores the LSB of the sequence timestamp for channel 8. The sequence timer value is the time assigned to the channel during the sequence triggered by ACT or SLEEP. The timestamp is stored when the voltage rising level passes the UV_LF[8] threshold for Power ON and Sleep Exit sequences (ACT 01 or SLEEP 01). The timestamp is stored when the voltage falling level passes the OFF threshold (200mV) for Power OFF and Sleep Entry sequences (ACT 10 or SLEEP 10). The least significant bit corresponds to 50µs (equal to tSEQ_LSB).

5.1.1.27 BANK_SEL Register (Offset = F0h) [Reset = X0h]

BANK_SEL is shown in Table 7-32.

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Bank Select.

Table 7-32 BANK_SEL Register Field Descriptions
BitFieldTypeResetDescription
7-1RESERVEDR0h Reserved
0BANK_SelectR/WXh Represents bank selection.
0 = Bank 0
1 = Bank 1

5.1.1.28 PROT1 Register (Offset = F1h) [Reset = X0h]

PROT1 is shown in Table 7-33.

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Locks or unlocks register changes. Must match PROT2.

Table 7-33 PROT1 Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR0h Reserved
5WRKCR/W0h Represents Protection from writes for WRKC group. Both PROT1 and PROT2 need to be set for protection.
0 = Changes to register are possible
1 = Changes to register are not possible
4RESERVEDR0h Reserved
3CFGR/WXh Represents Protection from writes for CFG group. Both PROT1 and PROT2 need to be set for protection.
0 = Changes to register are possible
1 = Changes to register are not possible
2IENR/WXh Represents Protection from writes for IEN group. Both PROT1 and PROT2 need to be set for protection.
0 = Changes to register are possible
1 = Changes to register are not possible
1MONR/WXh Represents Protection from writes for MON group. Both PROT1 and PROT2 need to be set for protection.
0 = Changes to register are possible
1 = Changes to register are not possible
0RESERVEDR0h Reserved

5.1.1.29 PROT2 Register (Offset = F2h) [Reset = X0h]

PROT2 is shown in Table 7-34.

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Locks or unlocks register changes. Must match PROT1.

Table 7-34 PROT2 Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR0h Reserved
5WRKCR/W0h Represents Protection from writes for CFG group. Both PROT1 and PROT2 need to be set for protection.
0 = Changes to register are possible
1 = Changes to register are not possible
4RESERVEDR0h Reserved
3CFGR/WXh Represents Protection from writes for CFG group. Both PROT1 and PROT2 need to be set for protection.
0 = Changes to register are possible
1 = Changes to register are not possible
2IENR/WXh Represents Protection from writes for IEN group. Both PROT1 and PROT2 need to be set for protection.
0 = Changes to register are possible
1 = Changes to register are not possible
1MONR/WXh Represents Protection from writes for MON group. Both PROT1 and PROT2 need to be set for protection.
0 = Changes to register are possible
1 = Changes to register are not possible
0RESERVEDR0h Reserved

5.1.1.30 PROT_MON Register (Offset = F3h) [Reset = X0h]

PROT_MON is shown in Table 7-35.

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Locks MON registers in tandem with PROT1 and PROT2.

Table 7-35 PROT_MON Register Field Descriptions
BitFieldTypeResetDescription
7MON[8]R/W0h Protects MON8 from writes along with PROT1 and PROT2.
0= Changes are possible
1= Changes are not possible
6MON[7]R/W0h Protects MON7 from writes along with PROT1 and PROT2.
0= Changes are possible
1= Changes are not possible
5MON[6]R/W0h Protects MON6 from writes along with PROT1 and PROT2.
0= Changes are possible
1= Changes are not possible
4MON[5]R/W0h Protects MON5 from writes along with PROT1 and PROT2.
0= Changes are possible
1= Changes are not possible
3MON[4]R/WXh Protects MON4 from writes along with PROT1 and PROT2.
0= Changes are possible
1= Changes are not possible
2MON[3]R/WXh Protects MON3 from writes along with PROT1 and PROT2.
0= Changes are possible
1= Changes are not possible
1MON[2]R/WXh Protects MON2 from writes along with PROT1 and PROT2.
0= Changes are possible
1= Changes are not possible
0MON[1]R/WXh Protects MON1 from writes along with PROT1 and PROT1.
0= Changes are possible
1= Changes are not possible

5.1.1.31 I2CADDR Register (Offset = F9h) [Reset = X0h]

I2CADDR is shown in Table 7-36.

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I2C Address

Table 7-36 I2CADDR Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0h Reserved
6-3ADDR_NVM[3:0]RXh Represents I2C address from internal OTP.
2-0ADDR_STRAP[2:0]RXh Represents I2C address from resistor value on ADDR pin.

5.1.1.32 DEV_CFG Register (Offset = FAh) [Reset = X0h]

DEV_CFG is shown in Table 7-37.

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Status of I2C interface voltage levels.

Table 7-37 DEV_CFG Register Field Descriptions
BitFieldTypeResetDescription
7-0RESERVEDR0h Reserved