SNVSCB5B March   2022  – May 2025 TPS388R0-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 I2C
      2. 7.3.2 Auto Mask (AMSK)
      3. 7.3.3 PEC
      4. 7.3.4 VDD
      5. 7.3.5 MON
      6. 7.3.6 NIRQ
      7. 7.3.7 NRST
    4. 7.4 Device Functional Modes
      1. 7.4.1 Built-In Self Test and Configuration Load
        1. 7.4.1.1 Notes on BIST Execution
      2. 7.4.2 TPS38800-Q1 Power ON
      3. 7.4.3 General Monitoring
        1. 7.4.3.1 IDLE Monitoring
        2. 7.4.3.2 ACTIVE Monitoring
        3. 7.4.3.3 Sequence Monitoring 1
          1. 7.4.3.3.1 ACT Transitions 0→1
          2. 7.4.3.3.2 SLEEP Transition 1→0
          3. 7.4.3.3.3 SLEEP Transition 0→1
        4. 7.4.3.4 Sequence Monitoring 2
          1. 7.4.3.4.1 ACT Transition 1→0
    5. 7.5 Register Maps
      1. 7.5.1 Registers Overview
        1. 7.5.1.1 BANK0 Registers
        2. 7.5.1.2 BANK1 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Multichannel Sequencer and Monitor
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
      4. 8.2.4 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Supply Guidelines
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Nomenclature
    2. 9.2 Documentation Support
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

7.4.3.2 ACTIVE Monitoring

The TPS38800-Q1/TPS388R0-Q1 is in ACTIVE state when ACT is High.

VMON monitors High Frequency channel levels against Under-Voltage High Frequency (UVHF) and Over-Voltage High Frequency (OVHF) thresholds.

Some channels can be connected to rails which are controlled by user software. Such channels can be in OFF state (below the OFF threshold) when the TPS38800-Q1/TPS388R0-Q1 is in ACTIVE state, and have the UVHF interrupts normally disabled. Once these rails are turned ON, the TPS38800-Q1/TPS388R0-Q1 host enables the channels UVHF interrupts to allow full monitoring. Similarly, before these rails are turned OFF, the TPS38800-Q1/TPS388R0-Q1 host disables the channels UVHF interrupts to avoid false UV violations during the ramp down. As these channels are not part of the sequencing initiated by ACT or SLEEP, UVHF/OVHF interrupts cannot be automatically enabled/disabled using the auto-mask registers.

Other enabled channels can be in OFF state as a result of the SLEEP 1→0 transition sequence. Those channels are identified by the AMSK_ENS auto-mask register, used to avoid UVHF and OVHF interrupts during the transition.

Table 7-3 Modes of Operation Summary
Mode Pin/Bit Condition Iq Monitored- Triggers NIRQ if CHx enabled Status only
ACTIVE ACT=High, Sleep=High 1.5mA OVHF, UVHF OFF
IDLE ACT=Low, Sleep=X 230uA OVHF OFF

SLEEP

ACT=High, SLEEP=Low

Sleep Power bit=1

 CHx not assigned to Sleep

1.5mA

 OVHF, UVHF OFF
CHx assigned to Sleep (AMSK=1) No monitoring OFF
CHx assigned to Sleep (AMSK=0) OVHF, UVHF OFF

DEEP SLEEP

ACT=High, SLEEP=Low

Sleep Power bit=0

 CHx not assigned to Sleep 330uA OVHF, UVHF -
CHx assigned to Sleep (AMSK=1) No monitoring -
CHx assigned to Sleep (AMSK=0) OVHF, UVHF -