SNVSCB5B March   2022  – May 2025 TPS388R0-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 I2C
      2. 7.3.2 Auto Mask (AMSK)
      3. 7.3.3 PEC
      4. 7.3.4 VDD
      5. 7.3.5 MON
      6. 7.3.6 NIRQ
      7. 7.3.7 NRST
    4. 7.4 Device Functional Modes
      1. 7.4.1 Built-In Self Test and Configuration Load
        1. 7.4.1.1 Notes on BIST Execution
      2. 7.4.2 TPS38800-Q1 Power ON
      3. 7.4.3 General Monitoring
        1. 7.4.3.1 IDLE Monitoring
        2. 7.4.3.2 ACTIVE Monitoring
        3. 7.4.3.3 Sequence Monitoring 1
          1. 7.4.3.3.1 ACT Transitions 0→1
          2. 7.4.3.3.2 SLEEP Transition 1→0
          3. 7.4.3.3.3 SLEEP Transition 0→1
        4. 7.4.3.4 Sequence Monitoring 2
          1. 7.4.3.4.1 ACT Transition 1→0
    5. 7.5 Register Maps
      1. 7.5.1 Registers Overview
        1. 7.5.1.1 BANK0 Registers
        2. 7.5.1.2 BANK1 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Multichannel Sequencer and Monitor
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
      4. 8.2.4 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Supply Guidelines
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Nomenclature
    2. 9.2 Documentation Support
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

6.5 Electrical Characteristics

At 2.6V <= VDD <= 5.5V, NIRQ,NRST Voltage = 10kΩ to VDD, NIRQ,NRST load = 10pF, and over the operating free-air temp range of – 40°C to 125°C, unless otherwise noted. Typical values are at TJ = 25°C, typical conditions at VDD= 3.3V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
COMMON PARAMETERS
VDD Input supply voltage  2.6 5.5 V
VDDUVLO Rising Threshold 2.67 2.81 V
Falling Threshold 2.48 2.60 V
VPOR Power on Reset Voltage (2) 1.65 V
IDD_Active Supply current into VDD pin (MON = HF active)
ACT = High, Sleep = High 
 		 VDD <= 5.5V  1.55 2 mA
IDD_Sleep Supply current into VDD pin (MON = HF active)
ACT = High ,Sleep = Low,I2C = Sleep power bit set to 1		 VDD <= 5.5V  1.55 2 mA
IDD_Idle Supply current into VDD pin 
ACT = Low, Idle state-I2C active and OVLF mon		 VDD <= 5.5V 
>10ms BIST		 200 280 µA
IDD_Deep Sleep Supply current into VDD pin (MON = HF active), ACT = High,Sleep = Low,I2C = Sleep power bit set to 0 VDD <= 5.5V  275 380 µA
VMONX MON voltage range 0.2 5.5 V
IMONX Input current MONx pins VMON = 5V 20 µA
IMONX_ADJ Input current for ADJ version (1x) VMON = 5V 0.1 µA
VMON_HF 1x mode (No scaling) 0.2 1.475 V
with 4x scaling 0.8 5.5 V
Threshold granularity_HF 1x mode (No scaling) LSB 5 mV
4x mode (With scaling) LSB 20 mV
Accuracy_HF VMON 0.2V≤VMONX≤1.0V –6 6 mV
1.0V<VMONX≤1.475V  -7.5 7.5 mV
1.475V<VMONX≤2.95V  -0.6 0.6 %
VMONX>2.95V  -0.5 0.5 %
VHYS_HF Hysteresis on UV,OV pin(Hysteresis is with respect of the tripoint ((UV),(OV))(1) 0.2V≤VMONX≤1.475V  5 11 mV
1.475V<VMONX≤2.95V  9 16
VMONX>2.95V 17 28 mV
VHYS_HF Hysteresis on UV,OV pin(Hysteresis is with respect of the tripoint ((UV),(OV))(1) Hysteresis disabled orderable 0 mV
MON_OFF OFF Voltage threshold Monitored falling edge of VMON 140 215 mV
ILKG Output leakage current -NIRQ VDD=VNIRQ=5.5V 300 nA
ACT_L Logic Low input  DEV_CONFIG.SOC_IF1=1 0.36 V
ACT_H Logic high input  DEV_CONFIG.SOC_IF1=1 0.84 V
SLEEP_L Logic Low input  DEV_CONFIG.SOC_IF1=1 0.36 V
SLEEP_H Logic high input  DEV_CONFIG.SOC_IF1=1 0.84 V
ACT Internal Pull down 100 kΩ
SLEEP Internal Pull down 100 kΩ
UV,OV Steps/Resolution 0.2V<VMONX≤1.475V 5 mV
0.8V<VMONX<5.5V 20
VOL Low level output voltage-NIRQ NIRQ ,5.5V/5mA 100 mV
Ilkg(OD) Open-Drain output leakage current-NIRQ NIRQ pin in High Impedance,VNIRQ = 5.5, Not asserted state 90 nA
VOL Low level output voltage-NRST NRST ,5.5V/5mA 100 mV
Ilkg(OD) Open-Drain output leakage current-NRST NRST pin in High Impedance,VNRST = 5.5, Not asserted state 90 nA
IADDR ADDR pin current 20 µA
I2C ADDR (Hex format) R=5.36k 0x30
R=16.2k 0x31
R=26.7k 0x32
R=37.4k 0x33
R=47.5k 0x34
R=59.0k 0x35
R=69.8k 0x36
R=80.6k 0x37
TSD Thermal Shutdown 155 ℃
TSD Hys Thernal Shutdown Hysterisis 20 ℃
RS Remote sense range -100 100 mV
I2C ELECTRICAL SPECIFICATIONS
CB Capacitive load for SDA and SCL 400 pF
SDA,SCL Low Threshold 1.2V config orderable 0.36 V
SDA,SCL High Threshold 1.2V config orderable 0.84 V
SDA,SCL Low Threshold 3.3V config orderable 0.99 V
SDA,SCL High Threshold 3.3V config orderable 2.31 V
SDA,SCL Low Threshold 1.8V config orderable 0.54 V
SDA,SCL High Threshold 1.8V config orderable 1.26 V
SDA VOL IOL=5mA 0.4 V
(1) Hysteresis is with respect of the tripoint (VIT-(UV), VIT+(OV)).
(2) VPOR is the minimum VDDX voltage level for a controlled output state.